Principal DFT Engineer

SambaNova Systems; San Jose, Austin (CA, TX); On-site; USD 180,000 - 255,000; Full time

Benefits offered by this job

Health insurance

Dental & Vision

Equity package

Job summary

SambaNova Systems in San Jose, CA seeks a Principal DFT Engineer to lead architecture and implementation of DFT for high-performance SoCs. You will oversee ATPG/MBIST flows, coverage analysis, and debug infrastructure across large hierarchical designs.

The role requires deep DFT knowledge, hands-on experience with Tessent or similar tools, and collaboration with STA and Physical Design to meet timing and yield goals. Equity and comprehensive benefits accompany a competitive package.

Qualifications

• B.S. in computer science, computer engineering, or related field.
• 10+ years relevant industry experience.
• Deep understanding of scan insertion, scan compression, ATPG, MBIST, JTAG, and hierarchical DFT.
• Hands-on experience with Siemens Tessent tool flow (preferred) or equivalent industry standard DFT tools.
• Familiarity with cell-aware ATPG, small-delay defects, IEEE 1500, IEEE 1687/IJTAG, and low-power DFT is highly desirable.
• Strong understanding of advanced ATPG, silicon diagnosis, and failure localization methodologies.
• Experience with STA constraints & analysis for DFT modes & SDF simulations.
• Working knowledge of Verilog/System-Verilog simulators & waveform debugging.

Responsibilities

• Define & implement block-level and SoC-level DFT architecture for large, hierarchical SoCs
• Develop and maintain ATPG flows for stuck-at, at-speed and advanced fault models.
• Develop scripts and automation for DFT insertion, ATPG, coverage analysis, pattern generation, and debug.
• Develop and maintain JTAG, IEEE 1500, and IEEE 1687/IJTAG infrastructure for internal test and debug access.
• Generate production-quality ATPG and MBIST patterns and support deployment to ATE.
• Work closely with STA and Physical Design teams on DFT timing closure
• Support silicon diagnosis, failure localization, yield analysis, and manufacturing test optimization.

Skills

ATPG

MBIST

JTAG

IEEE 1500/IJTAG

DFT architecture

Verilog/SystemVerilog

STA constraints

Waveform debugging

Diagnosis & failure localization

Education

B.S. in computer science, computer engineering, or related field

Tools

Siemens Tessent tool flow

Job description

About the role

Sambanova is looking for a talented and motivated Principal Design for Test (DFT) Engineer to help us build state-of-the-art RDU chips for machine learning and artificial intelligence.

We are looking for a highly hands-on engineer who will be responsible for DFT architecture and implementation, verification, ATPG, MBIST and silicon bring-up for complex high-performance chips.

Responsibilities

Your responsibilities will include:

• Define & implement block-level and SoC-level DFT architecture for large, hierarchical SoCs
• Develop and maintain ATPG flows for stuck-at, at-speed and advanced fault models.
• Develop scripts and automation for DFT insertion, ATPG, coverage analysis, pattern generation, and debug.
• Develop and maintain JTAG, IEEE 1500, and IEEE 1687/IJTAG infrastructure for internal test and debug access.
• Generate production-quality ATPG and MBIST patterns and support deployment to ATE.
• Work closely with STA and Physical Design teams on DFT timing closure
• Support silicon diagnosis, failure localization, yield analysis, and manufacturing test optimization.

Required Qualifications

• B.S. in computer science, computer engineering, or related field
• 10+ years relevant industry experience
• Deep understanding of scan insertion, scan compression, ATPG, MBIST, JTAG, and hierarchical DFT
• Hands-on experience with Siemens Tessent tool flow (preferred) or equivalent industry standard DFT tools
• Familiarity with cell-aware ATPG, small-delay defects, IEEE 1500, IEEE 1687/IJTAG, and low-power DFT is highly desirable
• Strong understanding of advanced ATPG, silicon diagnosis, and failure localization methodologies
• Experience with STA constraints & analysis for DFT modes & SDF simulations
• Working knowledge of Verilog/System-Verilog simulators & waveform debugging

Preferred Qualifications

• Experience with ATE pattern deployment and silicon bring-up
• Experience with multi-die/chiplet DFT, known-good-die test, or die-to-die interface testing
• Experience with large compute, AI accelerator, or HPC SoCs

Base Salary Range: Base Pay Range $180,000 — $255,000 USD

EEO Policy

SambaNova Systems is an Equal Opportunity/Affirmative Action Employer.

All qualified applicants will receive consideration for employment without regard basis of age (40 and over), color, disability, gender identity, genetic information, marital status, military or veteran status, national origin/ancestry, race, religion, creed, sex (including pregnancy, childbirth, breastfeeding), sexual orientation and any other applicable status protected by federal, state, or local laws.

Benefits Summary for US-Based, Full-Time Employment Positions

SambaNova offers a competitive total rewards package, including the base salary, plus equity and benefits.

We cover 95% premium coverage for employee medical insurance, and 77% premium coverage for dependents and offer a Health Savings Account (HSA) with employer contribution.

We also offer Dental, Vision, Short/Long term Disability, Basic Life, Voluntary Life, and AD&D insurance plans in addition to Flexible Spending Account (FSA) options like Health Care, Limited Purpose, and Dependent Care.

Our library of well-being benefits available to you and your dependents includes a full subscription to Headspace, Gympass+ membership with access to physical gyms, One Medical membership, counseling services with an Employee Assistance Program, and much more.