Principal RTL Design Engineer

Socket.dev; San Jose (CA); On-site; USD 180,000 - 255,000; Full time

Job summary

SambaNova Systems, based in the US, is seeking a Principal RTL Design Engineer to own microarchitecture and RTL for a major RDU block. You will drive hardware design from specification through tape-out, collaborating with architects, verification, and software teams to optimize timing, power, and area while mentoring others.

You will work with aggressive targets and contribute to advanced EDA flows, sharing responsibility for delivering high-performance AI accelerators.

Qualifications

• BS or MS in EE, CE, or CS with 7+ years of experience in ASIC RTL design.
• Mastery of synthesizable SystemVerilog for high-speed ASICs, including SVA.
• High-frequency design: datapath pipelining, retiming, timing targets.
• Deep foundation in computer architecture and digital logic design.
• Ownership of a complex block from spec through tape-out on production ASIC.
• Physical-design awareness: floorplan, congestion, timing feedback.
• Synthesis and static timing analysis, lint, CDC, LEC quality flows.
• Scripting in Python for design and flow automation.

Responsibilities

• Own microarchitecture and RTL implementation for a major block or subsystem of the RDU, from specification through tape-out
• Define and document microarchitecture specifications for complex digital blocks in compute, memory, or on-chip network subsystems
• Write, integrate, and debug synthesizable SystemVerilog RTL through the full chip implementation and production lifecycle
• Hit aggressive frequency targets through datapath pipelining, retiming, and microarchitectural restructuring
• Own PPA for your area: make and defend the power, performance, and area trade-offs using advanced techniques for high-speed design
• Drive timing closure with physical design: synthesis, STA, critical-path iteration, and response to floorplan and congestion feedback
• Own design quality gates for your area: lint, CDC, LEC, and SystemVerilog Assertions capturing design intent
• Partner with design verification to define verification intent and coverage for your block, and support debug of functional and gate-level failures
• Work with architects and software teams to prototype and evaluate features that improve application-level performance
• Drive AI, automation, and new EDA tool methodologies into the design flow
• Set the technical bar in design reviews and mentor design engineers

Skills

SystemVerilog

Python scripting

Microarchitecture design

RTL design

SVA

Synthesis & STA

Leadership without authority

Education

BS in EE/CE/CS

MS in EE/CE/CS

Job description

The era of pervasive AI has arrived. In this era, organizations will use generative AI to unlock hidden value in their data, accelerate processes, reduce costs, drive efficiency and innovation to fundamentally transform their businesses and operations at scale. SambaNova Suite™ is the first full-stack, generative AI platform, from chip to model, optimized for enterprise and government organizations. Powered by the intelligent SN40L chip, the SambaNova Suite is a fully integrated platform, delivered on-premises or in the cloud, combined with state-of-the-art open-source models that can be easily and securely fine-tuned using customer data for greater accuracy. Once adapted with customer data, customers retain model ownership in perpetuity, so they can turn generative AI into one of their most valuable assets.

About the team SambaNova's RDU is the processor behind our inference systems, and the RTL design team builds the blocks it's made of: compute datapath, on-chip network, and memory subsystems. The team owns microarchitecture through tape-out, including RTL implementation, PPA trade-offs, quality gates like lint, CDC, and LEC, and timing closure with physical design. Frequency targets are aggressive, so how a datapath gets pipelined and where area buys timing are decided here.

About the role SambaNova Systems is looking for a Principal RTL Design Engineer to own the microarchitecture and RTL for a major block or subsystem of our next-generation Reconfigurable Dataflow Unit, the silicon behind our AI workload acceleration systems. This is a senior individual-contributor role with real ownership. You'll take a block from microarchitecture specification through RTL, quality closure, and tape-out, and you'll own the power, performance, and area trade-offs along the way. Frequency targets here are aggressive, so the microarchitectural choices you make (how you pipeline a datapath, where you spend area to buy timing) are the substance of the job, not an afterthought. You'll work alongside architects, design verification, and physical design engineers to converge functionality and timing, and with software and compiler teams to prototype features that move application-level performance. You'll be one of the engineers who sets the technical bar for digital design here: in reviews, in the methodology the team adopts, and in how the design flow evolves.

Responsibilities

• Own microarchitecture and RTL implementation for a major block or subsystem of the RDU, from specification through tape-out
• Define and document microarchitecture specifications for complex digital blocks in compute, memory, or on-chip network subsystems
• Write, integrate, and debug synthesizable SystemVerilog RTL through the full chip implementation and production lifecycle
• Hit aggressive frequency targets through datapath pipelining, retiming, and microarchitectural restructuring
• Own PPA for your area: make and defend the power, performance, and area trade-offs using advanced techniques for high-speed design
• Drive timing closure with physical design: synthesis, STA, critical-path iteration, and response to floorplan and congestion feedback
• Own design quality gates for your area: lint, CDC, LEC, and SystemVerilog Assertions capturing design intent
• Partner with design verification to define verification intent and coverage for your block, and support debug of functional and gate-level failures
• Work with architects and software teams to prototype and evaluate features that improve application-level performance
• Drive AI, automation, and new EDA tool methodologies into the design flow
• Set the technical bar in design reviews and mentor design engineers

Required qualifications

• BS or MS in EE, CE, or CS with 7+ years (or equivalent) of industry experience in ASIC RTL design.
• Mastery of synthesizable SystemVerilog for high-speed, high-performance ASICs, including SVA to capture design intent.
• High-frequency design experience: datapath pipelining, retiming, critical-path restructuring, and other microarchitectural techniques for hitting aggressive frequency targets.
• Deep foundation in computer architecture and digital logic design: arbitration, flow control, clock domain crossing, and memory structures.
• Ownership of a complex block or subsystem from microarchitecture specification through tape-out on at least one production ASIC.
• Physical-design awareness: converging power, performance, and area against real physical constraints, including floorplan, congestion, and timing feedback from the physical design team.
• Hands-on experience with synthesis and static timing analysis, and with lint, CDC, and LEC quality flows.
• Demonstrated technical leadership without formal authority: setting direction in design reviews, arbitrating microarchitecture decisions, and mentoring engineers.
• Scripting in Python for design and flow automation.

Preferred qualifications

• Depth in one RDU domain: compute and dataflow datapath, on-chip network and interconnect, or memory subsystem.
• Industry-standard interconnects and protocols: AXI, PCIe, Ethernet, HBM/DDR AI and ML workload acceleration techniques, and dataflow or reconfigurable architectures.
• Formal property checking applied to design intent.
• Advanced TSMC nodes and multi-die or chiplet design.
• Performance modeling and analysis to support architectural trade-offs.
• Fluency with Claude or other AI tools applied to RTL design and flow development.
• MS or PhD in EE, CE, or CS with 10+ years of experience in ASIC RTL design.

Base Salary Range

Base Pay Range $180,000 — $255,000 USD

EEO Policy

SambaNova Systems is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard basis of age (40 and over), color, disability, gender identity, genetic information, marital status, military or veteran status, national origin/ancestry, race, religion, creed, sex (including pregnancy, childbirth, breastfeeding), sexual orientation, and any other applicable status protected by federal, state, or local laws.

Benefits Summary for US-Based, Full-Time Employment Positions

SambaNova offers a competitive total rewards package, including the base salary, plus equity and benefits. We cover 95% premium coverage for employee medical insurance, and 77% premium coverage for dependents and offer a Health Savings Account (HSA) with employer contribution. We also offer Dental, Vision, Short/Long term Disability, Basic Life, Voluntary Life, and AD&D insurance plans in addition to Flexible Spending Account (FSA) options like Health Care, Limited Purpose, and Dependent Care. Our library of well-being benefits available to you and your dependents includes a full subscription to Headspace, Gympass+ membership with access to physical gyms, One Medical membership, counseling services with an Employee Assistance Program, and much more.