Principal DFT Engineer

Celero Communications, Inc.; Irvine, Northern (CA, KY); Hybrid; USD 200,000 - 240,000; Full time

Job summary

Celero Communications, Inc. seeks a skilled DFT Engineer to partner with design, verification, and manufacturing teams to implement robust Design-for-Test methodologies for high-quality ASIC and SoC production.

You will develop DFT architecture, perform scan insertion and MBIST, and drive signoff and test readiness across silicon bring-up and yield improvement activities. The role requires 8+ years of DFT experience and strong tooling knowledge.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
• 8+ years of ASIC/SoC DFT experience.
• Strong understanding of scan, ATPG, fault models, and test coverage methodologies.
• Experience with Synopsys TestMAX/TetraMAX, DFT Compiler, Siemens Tessent, Cadence Modus, or equivalent tools.
• Knowledge of Verilog/SystemVerilog and digital design fundamentals.
• Experience in Linux and scripting using Python, Tcl, Perl, or Shell.
• Results-driven engineer with strong debugging abilities.
• Comfortable working in fast-paced cross-functional environments.
• Passion for delivering high-quality silicon products.

Responsibilities

• Develop and implement DFT architecture for ASIC and SoC designs.
• Perform scan insertion, scan chain planning, and scan compression implementation.
• Generate and validate ATPG patterns and analyze fault coverage results.
• Implement and verify MBIST, and other on-chip test features.
• Collaborate with RTL, verification, and physical design teams to ensure successful DFT integration.
• Support JTAG and boundary-scan implementation and debug.
• Drive DFT signoff activities and manufacturing test readiness.
• Participate in silicon bring-up, failure analysis, and yield improvement efforts.

Skills

DFT Architecture

ATPG/Scan

MBIST

JTAG/Boundary-scan

Verilog/SystemVerilog

Linux scripting

Cross-functional teamwork

High-quality silicon delivery

Education

Bachelor's degree in Electrical or Computer Engineering

Tools

Synopsys TestMAX

TetraMAX

Tessent

Cadence Modus

Job description

Celero Communications is seeking a talented DFT Engineer to join our silicon engineering organization. This individual will partner with design, verification, physical design, product, and manufacturing teams to implement robust Design-for-Test methodologies that enable high quality, high volume production of complex ASIC and SoC products.

What You Will Do

• Develop and implement DFT architecture for ASIC and SoC designs.
• Perform scan insertion, scan chain planning, and scan compression implementation.
• Generate and validate ATPG patterns and analyze fault coverage results.
• Implement and verify MBIST, and other on-chip test features.
• Collaborate with RTL, verification, and physical design teams to ensure successful DFT integration.
• Support JTAG and boundary-scan implementation and debug.
• Drive DFT signoff activities and manufacturing test readiness.
• Participate in silicon bring-up, failure analysis, and yield improvement efforts.

What You Will Bring

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
• 8+ years of ASIC/SoC DFT experience.
• Strong understanding of scan, ATPG, fault models, and test coverage methodologies.
• Experience with Synopsys TestMAX/TetraMAX, DFT Compiler, Siemens Tessent, Cadence Modus, or equivalent tools.
• Knowledge of Verilog/SystemVerilog and digital design fundamentals.
• Experience in Linux and scripting using Python, Tcl, Perl, or Shell.
• Results-driven engineer with strong debugging abilities.
• Comfortable working in fast-paced cross-functional environments.
• Passion for delivering high-quality silicon products.

Preferred Qualifications

• Experience with advanced-node semiconductor technologies.
• Hands-on experience with MBIST, compression architectures, and JTAG.
• Knowledge of timing closure, physical design impacts, and low-power design techniques.
• Experience supporting silicon validation and manufacturing production ramps.
• Strong communication and cross-functional collaboration skills. Annual Base Salary Range for US: $200,000 - $240,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)

Voluntary Self-Identification

For government reporting purposes, we ask candidates to respond to the below self-identification survey.Completion of the form is entirely voluntary. Whatever your decision, it will not be considered in the hiringprocess or thereafter. Any information that you do provide will be recorded and maintained in aconfidential file.

As set forth in Celero Communications, Inc.'s Equal Employment Opportunity policy, we do not discriminate on the basis of any protected group status under any applicable law.

If you believe you belong to any of the categories of protected veterans listed below, please indicate by making the appropriate selection. As a government contractor subject to the Vietnam Era Veterans Readjustment Assistance Act (VEVRAA), we request this information in order to measure the effectiveness of the outreach and positive recruitment efforts we undertake pursuant to VEVRAA. Classification of protected categories is as follows:

A "disabled veteran" is one of the following: a veteran of the U.S. military, ground, naval or air service who is entitled to compensation (or who but for the receipt of military retired pay would be entitled to compensation) under laws administered by the Secretary of Veterans Affairs; or a person who was discharged or released from active duty because of a service-connected disability.

A "recently separated veteran" means any veteran during the three-year period beginning on the date of such veteran's discharge or release from active duty in the U.S. military, ground, naval, or air service.

An "active duty wartime or campaign badge veteran" means a veteran who served on active duty in the U.S. military, ground, naval or air service during a war, or in a campaign or expedition for which a campaign badge has been authorized under the laws administered by the Department of Defense.

An "Armed forces service medal veteran" means a veteran who, while serving on active duty in the U.S. military, ground, naval or air service, participated in a United States military operation for which an Armed Forces service medal was awarded pursuant to Executive Order 12985.