Principal CAD Engineer - Digital/Analog IC Workflows

SiTime; Tempe (AZ); On-site; USD 161,000 - 230,000; Full time

Benefits offered by this job

401k plan

Health and wellness benefits (medical,

Dental coverage

Vision coverage

Life insurance

Parental leave

Equity grants

Time off plans

Job summary

SiTime is seeking a Principal Engineer, CAD to provide CAD software support for Digital, Analog and Mixed‑Signal designs using Cadence, Synopsys, Siemens, Keysight and third‑party tools. You will support RTL/ schematics, analog/mixed‑signal sims, layout, and Linux environments across multiple sites.

The role leads tool deployment, PDK validation, and tapeout coordination, interfacing with vendors to drive performance and reliability in a fast-paced team setting.

Qualifications

• Bachelor's degree in EE/CS or related field.
• 7+ years of CMOS IC CAD experience with analog and digital design.
• Experience with Cadence, Synopsys, Siemens, and Keysight toolsets.
• Proficiency in programming languages: DFII SKILL, PERL, MATLAB, Tcl/Tk, C/C++, Python.

Responsibilities

• Provide full lifecycle support for custom CAD flows across multiple toolchains.
• Own PDK installation, validation, and release management with foundries.
• Support tapeout flows, coordinating submissions to foundries and ensuring schedules.
• Support schematic capture, analog/mixed-signal sims, layout and DRC workflow.
• Develop CAD utilities, scripts and regression flows to improve design efficiency.
• Interface with EDA vendors for tool improvements and deployment.
• Prepare user documentation and training materials for design teams.

Skills

Communication skills

Team collaboration

Problem solving

Education

BA/BS Degree in Electrical Engineering, Computer Science or related field

Tools

Cadence Virtuoso

Spectre

Mobile/Physical layout tools

Innovus

Tempus

Questa

Parasitic CALIBRE PVS

DFII SKILL

PERL

MATLAB

Tcl/Tk

Python

Linux scripting

Job description

SiTime is seeking a Principal Engineer, CAD to provide CAD software support for Digital, Analog and Mixed‑Signal designs using Cadence, Synopsys, Siemens, Keysight and third‑party tools. You will support RTL/ schematics, analog/mixed‑signal sims, layout, and Linux environments across multiple sites.

The role leads tool deployment, PDK validation, and tapeout coordination, interfacing with vendors to drive performance and reliability in a fast-paced team setting.