Principal ASIC Design Engineer

Micron; Boise (ID); On-site; USD 140,000 - 200,000; Full time

Job summary

Micron Technology seeks a Principal ASIC Design Engineer to lead the RTL design and micro-architecture of high-speed digital blocks. You will own timing constraints, CDC strategies, and coordination with analog and layout teams to ensure successful tape-out of advanced interfaces.

You will verify RTL behavior, write SVA, and work with DV engineers to ensure robust silicon delivery.

Qualifications

• BS, MS, or PhD in Electrical Engineering or Computer Engineering.
• 7–12 years of ASIC design experience with at least one complete front-to-back tape-out.
• Proficiency in synthesizable SystemVerilog RTL design with clean, well-documented coding.
• Hands-on experience with logic synthesis and static timing analysis tools.
• Experience with RTL simulation and debug tools for block-level verification.

Responsibilities

• Own the micro-architecture and RTL implementation of all digital blocks in SystemVerilog.
• Define block specifications and CDC strategy; coordinate with analog/layout teams.
• Execute logic synthesis and drive timing closure across corners and modes.
• Interface with layout team for floorplanning constraints and design intent.
• Self-verify RTL using simulators; write SVA and collaborate with DV engineers.

Skills

SystemVerilog RTL design

Self-verification & debugging

Written communication

AI tools proficiency

Education

Electrical/Computer Engineering degree

Tools

Design Compiler

Cadence Genus

PrimeTime/Tempus

VCS/Xcelium

Verdi/DVE

SpyGlass/JasperGold

Job description

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Principal ASIC Design Engineer

About the Role

At Micron, we transform how the world uses information to enrich life for all. As a global leader in memory and storage innovation, we develop technologies that accelerate intelligence and enable the next era of AI, ML, and advanced computing.

Micron's Interface Pathfinding team drives performance-scaling innovation across circuits, signaling, packaging, and interconnects with a 3-5 year technology horizon. A core part of that work is silicon-based validation of novel PHY solutions, and we are growing the team to execute.

As the Principal ASIC Design Engineer, you will be the primary digital contributor on a deliberately small, senior team - united around the goal of carrying high-speed interface technologies from architecture to tape-out. The team's analog and chip-level architecture is anchored by a deeply experienced analog custom design engineer; your role is to be the authoritative digital voice - owning RTL design and micro-architecture of the digital blocks, defining timing constraints, supporting verification, and serving as the key interface between the digital design and the analog and layout specialists who will carry the implementation through to silicon. On a test ASIC of this scope, the front-end digital work is the critical path, with contractor and layout support engaged as bandwidth demands warrant.

What You'll Own

Digital Block Architecture & RTL Design

• Own the micro-architecture and RTL implementation of all digital soft IP blocks - CSR/register file, clocking control logic, management bus interfaces, and control state machines - in synthesizable SystemVerilog.
• Define and document block-level architecture specifications and interface control documents; serve as the authoritative reference for digital design intent.
• Define CDC strategy for digital blocks and ensure clean closure using standard analysis tools.
• Coordinate with the analog design lead on top-level chip integration, analog/digital partitioning, and chip boundary interface definitions.

Synthesis & Timing

• Execute logic synthesis (Synopsys Design Compiler or Cadence Genus) and drive optimization toward PPA targets.
• Develop and maintain block-level SDC constraints; execute and close static timing analysis (PrimeTime or Tempus) across required corners and modes.

Physical Design Interface

• Serve as the primary digital interface to the layout and implementation team - providing synthesized netlists, SDC constraints, floorplan guidance, and design intent documentation to enable effective physical implementation.
• Review and provide feedback on floorplan decisions, placement constraints, and timing closure results; partner with layout specialists to resolve implementation issues rooted in RTL or constraints.
• Coordinate with the verification team on scan chain insertion, DFT strategy, and ATPG planning.
• Where bandwidth and experience allow, participate directly in place-and-route and physical verification flows.

Self-Verification & Verification Support

• Self-verify RTL through block-level simulation (VCS or Xcelium), waveform debug (Verdi or DVE), and directed testing before engaging the verification team.
• Write SystemVerilog Assertions (SVA) for critical control sequences and protocol compliance.
• Collaborate with the Design Verification Engineer on the block-level verification plan, testbench coverage, and bug resolution.
• Support GLS and timing simulation using released netlists and SPF/parasitics; assist lab bring-up with simulation waveforms and register-level debug.

Documentation

• Maintain block specifications, SDC rationale, implementation guidance, and ECO history as institutional knowledge for follow-on chip development.

What You Bring

Required

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field
• 7-12 years of ASIC design experience with at least one complete front-to-back tape-out
• Proficiency in synthesizable SystemVerilog RTL design - linting-clean, well-documented coding practices
• Hands-on experience with logic synthesis (Design Compiler or Genus) and static timing analysis (PrimeTime or Tempus)
• Proficiency with RTL simulation and debug tools (VCS or Xcelium; Verdi or DVE) for block-level self-verification
• Solid understanding of CDC analysis methodologies (SpyGlass, JasperGold CDC, or equivalent)
• Ability to work effectively at the interface between digital design and custom/analog implementation teams - translating design intent into actionable guidance for layout and implementation specialists
• Strong written communication skills - this role produces specifications and documentation, not just code
• Proficiency in leveraging AI tools for productivity