Principal AMS Design Engineer - Implantable Neural ASIC

Epia Neuro; Alameda (CA); On-site; USD 225,000 - 280,000; Full time

Benefits offered by this job

Equity

Healthcare for dependents

Vacation policy

Parental leave

Alameda office

Job summary

Epia Neuro in Alameda, CA is seeking a Principal Design Engineer, Analog Mixed-Signal (AMS) to own the custom AMS ASIC at the heart of our implantable system. You will design critical analog blocks, drive tapeout and silicon bring-up, and lead a small team to deliver reliable, low-noise solutions for neural interfaces.

You will own chip architecture end to end, document design choices, and guide verification and post-silicon activities in a fast-paced, collaborative environment.

Qualifications

• 10+ years of hands-on AMS IC design experience.
• Led architecture or analog specification of at least one chip from concept to silicon.
• Deep transistor-level expertise in low-noise and ultra-low-power analog.
• Reliability-first design: ESD, device breakdown/SOA, aging, and yield.
• Fluency with Cadence Virtuoso/Spectre in a Linux-based design flow.
• MS or PhD in Electrical Engineering preferred.

Responsibilities

• Own the chip-level architecture and create a design specification.
• Document design choices, tradeoffs and verification results.
• Design critical analog/mixed-signal blocks and guide the rest.
• Run full verification: pre/post-layout, corners, Monte Carlo.
• Build Verilog-A/AMS and SystemVerilog models for verification.
• Lead design reviews and mentor engineers.
• Collaborate with layout, digital, system, and test teams and support post-silicon bring-up.

Skills

AMS IC design

Chip architecture

Transistor-level analog

Reliability-first design

Cadence Virtuoso/Spectre

Linux scripting environment

Education

BS/MS/PhD in Electrical Engineering

Tools

Cadence Virtuoso/Spectre

Job description

Epia Neuro in Alameda, CA is seeking a Principal Design Engineer, Analog Mixed-Signal (AMS) to own the custom AMS ASIC at the heart of our implantable system. You will design critical analog blocks, drive tapeout and silicon bring-up, and lead a small team to deliver reliable, low-noise solutions for neural interfaces.

You will own chip architecture end to end, document design choices, and guide verification and post-silicon activities in a fast-paced, collaborative environment.