Pre-Silicon SoC Modeling Lead (C++)

Amazon Web Services (AWS); Austin (TX); On-site; USD 168,100 - 227,400; Full time

Job summary

Annapurna Labs (U.S.) Inc. in Cupertino or Austin seeks a modeling engineer to build and own C++/SystemC models for SoCs powering ML accelerators.

You will translate architecture specs into testable models, validate against RTL, and develop regression suites and coverage-driven tests for pre-silicon verification.

Join a small, high-impact team with ownership and visible influence on chip design decisions.

Qualifications

• 6+ years of software development experience including design, reviews, and deployment.
• Experience mentoring or leading an engineering team.
• 6+ years creating functional or performance models of hardware (SoCs/ASICs/GPUs/CPUs/IP blocks).
• Proficiency in C++, with modern language features.
• Knowledge of SoC/CPU/GPU/ASIC architectures.

Responsibilities

• Build and own models translating architecture specs and RTL into accurate C++/SystemC models.
• Validate model behavior against RTL, debug discrepancies, and support pre-silicon verification flows.
• Develop model-based test infrastructure: regression suites, RTL correlation checks, and coverage-driven testing.
• Contribute to performance modeling efforts — building cycle-approximate models for design trade-offs before RTL exists.
• Improve modeling methodology and infrastructure across DV and architecture teams.
• Collaborate with chip architects to plan modeling work ahead of RTL availability.

Skills

C++ modeling

SystemC

DV verification

Performance modeling

Regression testing

Multi-threaded simulation

Mentoring / leadership

CI frameworks

Tools

CI frameworks

Job description

Annapurna Labs (U.S.) Inc. in Cupertino or Austin seeks a modeling engineer to build and own C++/SystemC models for SoCs powering ML accelerators.

You will translate architecture specs into testable models, validate against RTL, and develop regression suites and coverage-driven tests for pre-silicon verification.

Join a small, high-impact team with ownership and visible influence on chip design decisions.