Power & Performance Engineer for CPU/ASIC (Equity)

sifive

Santa Clara (CA)

On-site

USD 179,000 - 219,000

Full time

4 days ago
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Benefits offered by this job

Health insurance
Equity / stock options

Job summary

SiFive is seeking a power/architecture engineer to collect and analyze IP power, and work across teams to optimize design for state-of-the-art power efficiency. You will collect/analyze SiFive IP power consumption and collaborate with architecture and design to improve efficiency.

You will correlate power models with RTL and silicon, explore improvements to power analysis flows, and contribute to ASIC power optimization.

Qualifications

  • MS or PhD in Computer Science / Computer Architecture.
  • 3+ years of experience in power benchmarking, analysis and modeling.
  • Experience with power impacts at architecture, logic design, and circuit levels.
  • Good knowledge of computer architecture of high performance out-of-order CPU designs.
  • Working experience in guiding trade-off between performance and power to arrive at optimal design.
  • Experience with ASIC power analysis and optimization.
  • Hands‑on expertise with either HW development (RTL/implementation flows, verification/validation, backend flows, FPGA flows) or SW development is a strong plus.
  • Self‑starter, fast learner, strong problem‑solving skills.

Responsibilities

  • Collect / analyze SiFive IP power consumption.
  • Work with architecture and design to optimize our design to achieve state-of-the-art power efficiency
  • Correlate power models with RTL and Silicon
  • Innovate ways to improve power analysis flows

Skills

Power benchmarking
Power analysis
Power modeling
Computer architecture
ASIC power analysis

Education

MS or PhD in Computer Science / Computer Architecture

Job description

SiFive is seeking a power/architecture engineer to collect and analyze IP power, and work across teams to optimize design for state-of-the-art power efficiency. You will collect/analyze SiFive IP power consumption and collaborate with architecture and design to improve efficiency.

You will correlate power models with RTL and silicon, explore improvements to power analysis flows, and contribute to ASIC power optimization.

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