PLL IC Design Engineer – TeraWave

Anysilicon; San Diego, Northern (CA, KY); Hybrid; USD 140,000 - 190,000; Full time

Job summary

Blue Origin seeks an IC Design Engineer to lead PLL and clocking system development for advanced CMOS nodes and production cycles. You will own circuit design, layout oversight, and cross-team collaboration with RF and SOC architects to meet stringent space-related performance goals.

You will apply mixed-signal modeling in MATLAB/Spectre/SystemVerilog, iterate on VCOs, PFDs, and charge-pumps, and mentor junior engineers on analog design practices in a fast-paced, high-reliability environment.

Qualifications

• Bachelor's degree in Electrical Engineering or related technical discipline is required.
• 7+ years of experience in the design and development of fractional-N PLLs, DLLs, and sub-circuits in FinFET CMOS nodes such as 7nm or more advanced.
• Experience designing PLL building blocks such as VCOs, pre-scalers, PFDs, and charge-pumps.
• Experience with clock domain synchronization techniques across multiple PLLs and clock domains.
• Experience with clock distribution circuit design techniques (clock trees, frequency multipliers/dividers, CML buffers).
• Proficiency in mixed-mode modeling, simulation, and verification using MATLAB, Spectre, SystemVerilog, and AMS.
• Extensive experience in PLL silicon characterization and debugging.
• Proficiency in analog/RF building blocks including amplifiers, filters, clock buffers, and bias generators.
• Must be a U.S. citizen or eligible to work in the U.S.

Responsibilities

• Own the system and circuit design of PLLs and clock distribution circuits in advanced CMOS technologies, focusing on performance optimization and trade-off analysis.
• Utilize proficiency in Spectre and AMS flows to develop high-performance PLL circuits.
• Collaborate with RF and SOC architects and chip leads to define requirements based on system specifications.
• Oversee layout, top-level integration, floorplanning, and verification for tape-out readiness.
• Work with validation and product engineers to develop test plans, bring-up, optimize performance, and ensure high-yield production cycles.
• Investigate and implement fundamental analog building blocks to enhance circuit performance.
• Mentor junior engineers for best design practices in the analog domain.

Skills

PLL design

Clock distribution

AMS flows

SystemVerilog

MATLAB

Spectre

VCOs

PFDs/CPs

FinFET CMOS

Silicon debugging

Education

Bachelor's degree in Electrical Engineering

Tools

Spectre

SystemVerilog

AMS

MATLAB

Cadence

Job description

Blue Origin is seeking an IC Design Engineer to contribute to the development of integrated Phase-Locked Loops (PLLs) and clocking systems for its innovative satellite communications network, TeraWave. This role is crucial for enhancing technology offerings in space communication systems, aligning with Blue Origin's mission to enable millions to live and work in space for the benefit of Earth.

Responsibilities:

• Own the system and circuit design of PLLs and clock distribution circuits in advanced CMOS technologies, focusing on performance optimization and trade‑off analysis.
• Utilize full proficiency in Spectre and AMS flows to develop high‑performance PLL circuits.
• Collaborate with RF and SOC system architects and chip leads to define requirements for PLLs and their sub‑blocks based on system specifications.
• Oversee layout, top‑level integration, floorplanning, and verification of the overall design for successful tape‑out cycle.
• Work closely with validation and product engineers to develop test plans, facilitate bring‑up, optimize performance, and ensure reliable & high‑yield production cycles.
• Investigate and implement fundamental analog building blocks to enhance overall circuit performance.
• Mentor junior engineers for best design practices in the analog domain.

Qualifications:

• Bachelor's degree in Electrical Engineering or related technical discipline.
• 7+ years of experience in the design and development of fractional‑N PLLs, DLLs, and their sub‑circuits in FinFET CMOS nodes such as 7n or more advanced.
• Extensive experience in the design of PLL building blocks such as VCOs, high‑speed integer and frac‑N pre‑scalers, PFDs, charge‑pumps, etc.
• Experience with clock domain synchronization techniques within systems involving multiple PLLs and/or clock domains.
• Experience with clock distribution circuit design techniques and optimization, including clock trees, frequency multipliers and dividers, CML buffers, inductive peaking, etc.
• Full proficiency in mixed‑mode modeling, simulation, and verification methodologies using toolsets such as MATLAB, Spectre, SystemVerilog, and AMS.
• Extensive experience in PLL silicon characterization and debugging.
• Proficiency in the design of fundamental analog/RF building blocks, including amplifiers, filters, clock buffers, and bias generators.
• Must be a U.S. citizen or national, U.S. permanent resident, or lawfully admitted into the U.S. as a refugee or granted asylum.

Skills:

• Strong expertise in loop design for phase noise/jitter, spur profile, area, and power optimization.
• Experience designing All‑Digital PLLs (ADPLL) and/or sub‑sampling PLLs is a plus.
• Experience with fundamental analog building blocks such as LDOs and operational amplifiers.
• Fundamental understanding of device physics for process selection and performance optimization.
• Familiarity with digital design, digital verification, and SystemVerilog modeling.

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