Physical Design Engineer, TPU

Google Inc.; Sunnyvale (CA); On-site; USD 156,000 - 229,000; Full time

Job summary

Join a forward-thinking company and shape the future of AI/ML hardware acceleration. This role offers the opportunity to drive cutting-edge TPU technology, contributing to innovative silicon solutions that power applications loved by millions. You will leverage your design and verification expertise to verify complex digital designs, focusing on TPU architecture within AI/ML systems. Be part of a team that prioritizes security, efficiency, and reliability while making a global impact across software and hardware. If you're passionate about technology and eager to make a difference, this role is perfect for you.

Qualifications

• 7 years of experience in physical design with silicon-based ICs.
• Expertise in logic synthesis and timing analysis.

Responsibilities

• Drive physical implementation of complex ASICs at various levels.
• Oversee physical design of internal and third-party IPs.

Skills

Physical design experience

Logic synthesis

PnR

Timing closure

Static timing analysis

Education

Bachelor's degree in Electrical Engineering

Master's degree or PhD in Electrical Engineering

Tools

Industry-standard tools for IC design

Job description

corporate_fare Google place Sunnyvale, CA, USA

Apply

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 7 years of physical design experience with industry-standard tools, languages, and methodologies relevant to the development of silicon-based ICs and chips.
• Experience in logic synthesis, PnR, timing closure, and static timing analysis.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience managing external vendors.
• Experience with compute cores, high-speed memory technologies, silicon interposer design and advanced packaging technologies.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .

Responsibilities

• Drive the physical implementation of complex ASICs in advanced technology nodes at floorplan block, subsystem, and chip levels.
• Oversee physical design of internal IPs and third-party IPs, including digital logic, I/Os, analog PHYs, etc.
• Setup and/or review constraints for synthesis, STA, CDC, and RDC.
• Plan/review floorplan and provide feedback.
• Set up PD flows, participate in co-design. Be a liaison between internal design teams and external vendors, track PD progress via checklists and help resolve PD issues.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.