Physical Design Engineer, TPU

Google; Sunnyvale (CA); On-site; USD 156,000 - 229,000; Full time

Job summary

An established industry player is seeking a talented engineer to shape the future of AI/ML hardware acceleration. In this exciting role, you'll drive the development of cutting-edge TPU technology that powers transformative applications. You'll collaborate with a dynamic team, pushing the boundaries of custom silicon solutions while ensuring the highest standards of design and verification. This position offers a unique opportunity to contribute to innovative projects that impact millions globally, all within a vibrant and inclusive work culture. If you're passionate about technology and eager to make a difference, this role is perfect for you.

Benefits

Bonus

Equity

Health benefits

Qualifications

• 7+ years of physical design experience with silicon-based ICs and chips.
• Bachelor's degree or equivalent practical experience required.

Responsibilities

• Drive physical implementation of complex ASICs in advanced technology nodes.
• Oversee physical design of internal and third-party IPs.

Skills

Physical design experience

Logic synthesis

PnR

Timing closure

Static timing analysis

Vendor management

Education

Bachelor's degree in Electrical Engineering

Master's degree or PhD in Electrical Engineering

Tools

Industry-standard design tools

Job description

corporate_fare Google place Sunnyvale, CA, USA

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Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 7 years of physical design experience with industry-standard tools, languages, and methodologies relevant to the development of silicon-based ICs and chips.
• Experience in logic synthesis, PnR, timing closure, and static timing analysis.

Preferred Qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience managing external vendors.
• Experience with compute cores, high-speed memory technologies, silicon interposer design and advanced packaging technologies.

About the Job:

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities:

• Drive the physical implementation of complex ASICs in advanced technology nodes at floorplan block, subsystem, and chip levels.
• Oversee physical design of internal IPs and third-party IPs, including digital logic, I/Os, analog PHYs, etc.
• Setup and/or review constraints for synthesis, STA, CDC, and RDC.
• Plan/review floorplan and provide feedback.
• Set up PD flows, participate in co-design. Be a liaison between internal design teams and external vendors, track PD progress via checklists and help resolve PD issues.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.