Intern, Physical Design & DFT

Tenstorrent; Santa Clara (CA); On-site; USD 69,000 - 96,000; Full time

Job summary

Tenstorrent is seeking interns for RTL-centric work and physical design objectives. You will contribute to synthesis, floorplanning, place & route, and timing closure, while exploring ML-assisted physical design and DFT concepts such as JTAG, ATPG, and MBIST.

The position offers exposure to a commercial PnR toolchain, hands-on learning of timing/power/area tradeoffs, and teamwork across hardware and software domains. On-site opportunities in multiple U.S. locations.

Qualifications

• Pursuing a BS, MS, or PhD in Electrical or Computer Engineering, Computer Science, or Software Engineering.

Responsibilities

• Physical Design: Synthesis, floorplanning, place & route, clocking, timing closure.
• Advanced Physical Design: ML-assisted design flows.
• DFT: JTAG, Scan/ATP, MBIST.
• Gain hands-on experience in Design-for-Testability (DFT) to enable efficient testing.

Education

BS, MS, or PhD in Electrical or Computer Engineering, Computer Science, Software Engineering

Tools

Synopsys

Cadence

Job description

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Overview:

This is where verified RTL becomes an actual, manufacturable chip. Every timing constraint, every power tradeoff, every Design For Test (DFT) decision here determines whether the silicon works when it comes back from the fab.

What you might work on:

• Physical Design: Synthesis, floorplanning, place & route, clocking, timing closure.
• Advanced Physical Design: ML-assisted approaches to physical design flows.
• DFT: Design hardware to enable structural post-silicon test. JTAG, Scan/ATPG, MBIST.

This role is on-site, based out of Austin, TX or Boston, MA or Fort Collins, CO or Santa Clara, CA.

Who You Are

• Currently pursuing a BS, MS, or PhD in Electrical or Computer Engineering, Computer Science, Software Engineering.
• Solid understanding of logic design, VLSI, and transistor-level concepts.
• Familiarity with PnR tools, timing analysis, and power optimization techniques.
• Familiarity with JTAG, MBIST, and scan concepts.
• Comfortable scripting in Tcl, Perl, Shell, or Python.

What We Need

• Hands-on experience with a commercial PnR toolchain (Synopsys, Cadence).
• Coursework or projects in DFT, test methodology, VLSI or digital design, computer architecture.
• Interest or exposure with AI tools to accelerate development and workflows.

What You Will Learn

• The physical design flow, from RTL handoff to final tapeout.
• Timing, power, EM/IR, and area tradeoffs at the chip level.
• Industry-standard EDA tools and flows used in modern chip development.
• Gain hands-on experience in Design-for-Testability (DFT) to enable efficient testing.

USA Hiring Timelines

This internship opportunity is available throughout our 3 terms with the following corresponding recruitment cycles:

• Winter Term: Jan–Apr work term, Sept–Dec recruit.
• Summer Term: May–Aug work term, Oct–Apr recruit.
• Fall Term: Sept–Dec work term, Jan–Aug recruit.

Please note these timelines are for reference only. Actual timelines may vary.

Compensation for all interns at Tenstorrent ranges from $50/hr - $70/hr including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.