Design Verification Engineer, Silicon

Meta; Redmond (WA); On-site; USD 146,000 - 209,000; Full time

Job summary

Meta Reality Labs is seeking a Design Verification Engineer for its silicon team in Redmond, WA. You will verify complex AR/VR chips and develop verification strategies, collaborating with design, architecture, and software teams to bring high-performance silicon from spec to tape-out.

The role emphasizes constrained-random UVM testbenches, functional coverage, formal verification, and post-silicon handoff with firmware.

Qualifications

• Bachelor’s degree in Computer Science, Computer Engineering, or a related field.
• 6+ years of digital design verification experience.
• 6+ years with SystemVerilog and/or VHDL.
• Experience creating and closing functional coverage models and code coverage metrics.
• Proficiency with Python or Perl for test automation.

Responsibilities

• Develop and own verification plans for digital blocks and subsystems.
• Design and implement constrained-random UVM testbenches for RTL designs.
• Define functional and code coverage and track coverage closure.
• Collaborate with RTL engineers to review microarchitecture specs and mitigate risks.
• Develop and maintain simulation infrastructure, regression frameworks, and CI test suites.
• Perform formal verification and property checking to complement simulations.
• Debug failing simulations via waveforms and logs to root-cause issues.
• Partner with post-silicon validation and firmware teams for pre-silicon test content.
• Contribute to verification methodology improvements and reusable IP.
• Track progress and report risks to design and program management.

Skills

Constrained-random verification

UVM-based testbenches

Python scripting

Debugging RTL

Collaboration with RTL teams

Education

Bachelor's degree in Computer Science/Engineering or related field

Tools

SystemVerilog

VHDL

UVM

Job description

Meta Reality Labs is building custom silicon to power the next generation of augmented and virtual reality devices, including headsets and wearables. As a Design Verification Engineer on the silicon team, you will be responsible for ensuring the functional correctness and quality of complex custom chips that enable immersive AR/VR experiences. In this role, you will develop and execute comprehensive verification strategies for digital logic blocks and subsystems, working closely with design, architecture, and software teams to bring high-performance, low-power silicon from specification to tape-out.

Design Verification Engineer, Silicon Responsibilities:

• Develop and own verification plans for digital logic blocks and subsystems within custom AR/VR silicon, covering functional coverage, corner cases, and compliance requirements
• Design and implement constrained-random UVM testbenches to verify complex RTL designs including processors, interconnects, memory controllers, and multimedia accelerators
• Define and close functional coverage models and code coverage metrics to ensure thorough verification of design intent
• Collaborate with RTL design engineers to review microarchitecture specifications and identify verification risks early in the design cycle
• Develop and maintain simulation infrastructure, regression frameworks, and automated test suites to support continuous integration of design changes
• Perform formal verification and property checking on critical design blocks to complement simulation-based verification
• Debug failing simulations and regressions by analyzing waveforms, log files, and RTL code to root-cause design or testbench issues
• Partner with post-silicon validation and firmware teams to develop pre-silicon test content that transitions to hardware bring-up
• Contribute to verification methodology improvements, including reusable verification IP and shared infrastructure across the silicon team
• Track and report verification progress, coverage closure status, and risk areas to design and program management stakeholders

Minimum Qualifications:

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• 6+ years of experience in digital design verification, including development of UVM-based constrained-random testbenches for complex RTL blocks or subsystems
• 6+ years of experience with hardware description and verification languages including SystemVerilog and/or VHDL
• Experience defining and closing functional coverage models and code coverage metrics for complex digital designs
• Experience debugging RTL simulations using waveform analysis tools and log-based root-cause analysis
• Experience with scripting languages such as Python or Perl for test automation, regression management, or coverage analysis

Preferred Qualifications:

• Experience with post-silicon validation, hardware bring-up, or transitioning pre-silicon test content to physical hardware
• Experience verifying silicon for mobile, wearable, or consumer electronics SoCs, including low-power design verification techniques
• Knowledge of AR/VR-relevant subsystems such as Computer Vision , image signal processors, or neural network accelerators
• Familiarity with formal verification tools and methodologies such as property checking or equivalence checking

About Meta:

Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.

Meta is proud to be an Equal Employment Opportunity and Affiantive Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [e-mail].

$146,000/year to $209,000/year + bonus + equity + benefits Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.