Physical Design Engineer II (Silicon Engineering)

SPACE EXPLORATION TECHNOLOGIES CORP; Bastrop (TX); On-site; USD 100,000 - 120,000; Full time

Job summary

SPACE EXPLORATION TECHNOLOGIES CORP, located in Bastrop, TX, is seeking a Physical Design Engineer II to participate in the development of cutting-edge ASICs for deployment in space and ground infrastructures. The ideal candidate will have a Bachelor's degree in electrical engineering, computer engineering, or computer science, alongside 3+ years of relevant experience. Responsibilities include performing physical implementation steps, improving design methodologies, and collaborating with cross-disciplinary teams. A dynamic work environment fosters growth and innovation.

Qualifications

• 3+ years of professional experience in physical design flow development.
• Strong understanding of deep sub-micron FinFET and CMOS solid state physics.
• Experience with CMOS analog circuit and physical design.

Responsibilities

• Perform partition synthesis and physical implementation steps.
• Develop physical design methodologies and automation scripts.
• Collaborate with the ASIC design team on architectural feasibility.

Skills

RTL2GDSII physical design

EDA tools proficiency

CMOS digital design principles

Physical design methodologies

Static timing analysis (STA)

Education

Bachelor’s degree in electrical engineering, computer engineering or computer science

Tools

Deep sub‑micron and CMOS tools

Job description

Physical Design Engineer II (Silicon Engineering)

Bastrop, TX

SpaceX was founded under the belief that a future where humanity is exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world‑class cross‑disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation) in developing cutting‑edge next‑generation ASICs for deployment in space and ground infrastructures around the globe. These chips enable connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting‑edge solutions that will expand the performance and capabilities of the Starlink network.

RESPONSIBILITIES:

• Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
• Develop/improve physical design methodologies and automation scripts for various implementation steps
• Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
• Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution
• Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering or computer science
• 3+ years of professional experience working on RTL2GDSII physical design and/or physical design flow development

PREFERRED SKILLS AND EXPERIENCE:

• Experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms
• Knowledge of deep sub‑micron FinFET and CMOS solid state physics
• Understanding of CMOS digital design principles, basic standard cells and their functionality, standard cell libraries
• Understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
• Familiar with CMOS analog circuit and physical design
• Basic knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows
• Self‑driven individual with a can‑do attitude, willing to learn, and an ability to work in a dynamic group environment

ADDITIONAL REQUIREMENTS:

• Ability to work extended hours and weekends as needed to meet critical project milestones.
• To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful permanent resident (green card holder), (iii) refugee under 8 U.S.C. § 1157, or (iv) asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR.

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

Applicants wishing to view a copy of SpaceX’s affirmative action plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to [e-mail].