Physical Design Engineer

Qualcomm; Santa Clara (CA); On-site; USD 190,000 - 285,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking experienced Physical Design Engineers to contribute to cutting-edge SoC and ASIC projects across AI, mobile, automotive, data center and more.

You will participate in floorplanning, CTS, low-power techniques, timing analysis, and automated design flows, collaborating with architecture and verification teams. The role emphasizes developing innovative PD methodologies, scripting tools, and sign-off readiness, with opportunities to work on multiple nodes and

Qualifications

• Bachelor�s or Master�s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 6+ years of ASIC design/verification experience or related work.
• Experience with Cadence Innovus and Synopsys Fusion Compiler is preferred.
• Strong scripting skills in Python, Perl, TCL, Shell.

Responsibilities

• Lead physical design flow from netlist to tape-out.
• Develop solutions for high-speed, low-power ASICs/SoCs.
• Perform floorplanning, CTS, routing, timing closure across MMMC scenarios.
• Analyze timing, signal integrity, and PD rule violations; drive ECOs.

Skills

Physical Design

Floorplanning

CTS

Timing Analysis

Scripting (Python/TCL)

Education

BS in Electrical/Computer Engineering

MS in Electrical/Computer Engineering

PhD in relevant field

Tools

Cadence Innovus

Synopsys Fusion Compiler

PrimeTime SI

Job description

Company

Qualcomm Technologies, Inc.

Job Area

Engineering Group, Engineering Group > ASICS Engineering

Job Description

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drive communication and data processing transformation, helping create a smarter, more connected future for all.

Qualcomm is seeking talented Physical Design Engineers to join our growing SoC and ASIC Design organization. Successful candidates will have the opportunity to contribute across a variety of projects spanning high-performance computing, AI, mobile, automotive, data center, and next-generation semiconductor technologies. Engineers in this role may work on different aspects of Physical Design ASIC and SoC development, including floorplan, Clock Tree Synthesis, low power implementation, timing analysis, design methodology, automation and enabling new technology nodes.

This is an excellent opportunity to join a fast-paced engineering team developing leading-edge products on advanced process technologies while collaborating with world-class design, verification, implementation, and physical design teams.

Key Responsibilities

• Execute and drive all stages of the physical design flow from synthesized netlist to tape-out.
• Develop and implement physical design solutions for complex, high-speed, and low-power ASICs and SoCs.
• Perform floorplanning, partitioning, power planning, and IR-drop analysis.
• Execute placement, clock tree synthesis (CTS), routing, timing optimization, and timing closure across Multi-Mode Multi-Corner (MMMC) scenarios.
• Analyze and resolve timing violations, signal integrity issues, crosstalk effects, and physical design rule violations.
• Perform RC extraction, physical verification, and formal verification activities.
• Implement engineering change orders (ECOs) and support design convergence through sign-off.
• Collaborate with architecture, RTL, DFT, verification, and methodology teams to ensure successful project execution.
• Contribute to the development of innovative low-power implementation methodologies and customized place-and-route solutions.
• Develop automation and productivity tools using scripting languages and software development techniques.

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• 10+ years of industry experience or relevant academic/project experience in Physical Design.

Preferred Qualifications

• Experience in one or more of the following areas:
• ASIC/SoC Physical Design implementation.
• Place and Route using Cadence Innovus and/or Synopsys Fusion Compiler.
• Static Timing Analysis and timing closure using Synopsys PrimeTime SI.
• Physical verification and design sign-off methodologies.
• Formal verification techniques and tools.
• Power domain implementation and low-power design methodologies.
• Clock Tree Synthesis (CTS), routing, and timing optimization.
• Low power implementation techniques experience
• Signal integrity, noise analysis, and MMMC sign-off flows.
• DFT-aware physical implementation and constraint management.
• Programming and automation using Python, Perl, TCL, Shell scripting, C/C++, and Linux/Unix environments.
• Perl/Tcl, Python skills are needed.
• Strong problem solving and ASIC development/debugging skills.

Minimum Qualifications

• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.

OR

Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.

OR

PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [e-mail] or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

EEO Employer

Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

Pay Range And Other Compensation & Benefits

$190,200.00 - $285,400.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.

If you would like more information about this role, please contact Qualcomm Careers.