Physical Design Engineer

Acceler8 Talent; Mountain View (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Acceler8 Talent is partnering with a stealth AI infrastructure startup to hire a senior physical design engineer for AI accelerators. You will own the physical design from floorplan to signoff and drive synthesis, CTS, timing closure, and ECOs to production silicon.

You will collaborate with architecture, RTL, verification, foundry, and EDA teams to tackle complex timing, congestion, and power challenges using AI-assisted design flows.

Qualifications

• 8+ years of hands-on physical design experience on advanced ASIC or SoC programs.
• End-to-end ownership of physical implementation from floorplan through signoff.
• Strong experience with synthesis, place & route, CTS, timing closure, and physical optimisation.
• Experience delivering production silicon at advanced process nodes (7nm or below).
• Expertise using tools such as Cadence Innovus, Synopsys Fusion Compiler, PrimeTime, or Tempus.

Responsibilities

• Owning physical design from floorplan through signoff for AI accelerator silicon.
• Driving synthesis, place & route, clock tree synthesis, timing closure, and ECO implementation.
• Working closely with architecture, RTL, verification, foundry, and EDA teams to deliver production silicon.
• Solving complex timing, congestion, power, and physical implementation challenges.
• Using AI-assisted design flows to improve engineering productivity and tapeout execution.
• Helping shape the physical implementation methodology for next-generation AI accelerators.

Skills

Physical Design

Floorplanning

Place & Route

Clock Tree Synthesis

Timing Closure

Cadence Innovus

Synopsys Fusion Compiler

PrimeTime

Tempus

7nm or below process nodes

Tools

Cadence Innovus

Synopsys Fusion Compiler

PrimeTime

Tempus

Job description

I'm working with a stealth AI infrastructure startup founded by the engineers behind Tesla Dojo, Apple Silicon, AMD Zen, and Cerebras.

They're building a fundamentally new computing platform designed to solve one of AI's biggest infrastructure challenges: scaling performance without scaling power consumption and cost.

Using wafer-scale architectures and advanced 3D integration, they're rethinking how AI compute is built from the silicon up - reducing data movement, increasing compute density, and enabling the next generation of AI training and inference.

This is an opportunity to join a small, world-class engineering team building cutting-edge AI hardware from first principles.

You'll work on

• Owning physical design from floorplan through signoff for AI accelerator silicon
• Driving synthesis, place & route, clock tree synthesis, timing closure, and ECO implementation
• Working closely with architecture, RTL, verification, foundry, and EDA teams to deliver production silicon
• Solving complex timing, congestion, power, and physical implementation challenges
• Using AI-assisted design flows to improve engineering productivity and tapeout execution
• Helping shape the physical implementation methodology for next-generation AI accelerators.

We're looking for engineers who have

• 8+ years of hands-on physical design experience on advanced ASIC or SoC programs
• End-to-end ownership of physical implementation from floorplan through signoff
• Strong experience with synthesis, place & route, CTS, timing closure, and physical optimisation
• Experience delivering production silicon at advanced process nodes (7nm or below)
• Expertise using tools such as Cadence Innovus, Synopsys Fusion Compiler, PrimeTime, or Tempus
• A track record of solving difficult implementation challenges across architecture, RTL, and physical design teams

Particularly relevant experience includes

• Physical Design
• Floorplanning
• Place & Route
• Clock Tree Synthesis (CTS)
• Timing Closure
• Cadence Innovus
• Synopsys Fusion Compiler
• AI Accelerators
• Tapeout

Nice to have

• GPU, CPU, AI accelerator, or datacenter silicon experience
• CoWoS, 2.5D or 3D packaging
• IR/EM or signal integrity analysis
• DFT-aware physical implementation
• Experience working directly with foundries and EDA vendors

If you're interested in building the next generation of AI hardware alongside engineers who've developed some of the industry's most advanced compute platforms, I'd love to chat.