Senior AI Accelerator Physical Design Engineer

Acceler8 Talent; Mountain View (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Acceler8 Talent is partnering with a stealth AI infrastructure startup to hire a senior physical design engineer for AI accelerators. You will own the physical design from floorplan to signoff and drive synthesis, CTS, timing closure, and ECOs to production silicon.

You will collaborate with architecture, RTL, verification, foundry, and EDA teams to tackle complex timing, congestion, and power challenges using AI-assisted design flows.

Qualifications

• 8+ years of hands-on physical design experience on advanced ASIC or SoC programs.
• End-to-end ownership of physical implementation from floorplan through signoff.
• Strong experience with synthesis, place & route, CTS, timing closure, and physical optimisation.
• Experience delivering production silicon at advanced process nodes (7nm or below).
• Expertise using tools such as Cadence Innovus, Synopsys Fusion Compiler, PrimeTime, or Tempus.

Responsibilities

• Owning physical design from floorplan through signoff for AI accelerator silicon.
• Driving synthesis, place & route, clock tree synthesis, timing closure, and ECO implementation.
• Working closely with architecture, RTL, verification, foundry, and EDA teams to deliver production silicon.
• Solving complex timing, congestion, power, and physical implementation challenges.
• Using AI-assisted design flows to improve engineering productivity and tapeout execution.
• Helping shape the physical implementation methodology for next-generation AI accelerators.

Skills

Physical Design

Floorplanning

Place & Route

Clock Tree Synthesis

Timing Closure

Cadence Innovus

Synopsys Fusion Compiler

PrimeTime

Tempus

7nm or below process nodes

Tools

Cadence Innovus

Synopsys Fusion Compiler

PrimeTime

Tempus

Job description

Acceler8 Talent is partnering with a stealth AI infrastructure startup to hire a senior physical design engineer for AI accelerators. You will own the physical design from floorplan to signoff and drive synthesis, CTS, timing closure, and ECOs to production silicon.

You will collaborate with architecture, RTL, verification, foundry, and EDA teams to tackle complex timing, congestion, and power challenges using AI-assisted design flows.