Physical Design Engineer

Apple Inc.; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Apple employee benefits

Job summary

Apple Inc. in Austin, TX is seeking an electronics design engineer to close physical design, optimize power and timing, and drive design closure from partition to SOC level.

You will use tools like Innovus and Primetime to floorplan, place and route, and verify timing, while analyzing power, area, and DRC constraints to improve QoR. The role requires a Master’s degree in Electrical Engineering or related field with 3 years of related experience and strong scripting skills in Tcl, Perl, or

Qualifications

• Master’s degree in Electrical Engineering or related field.
• 3 years of experience in the job offered or related occupation.
• Experience with physical design closure tools and flows.
• Experience scripting in Tcl, Perl, or Python to accelerate design work.
• Experience optimizing power, timing, and area for QoR improvements.
• Familiarity with clock tree optimization and timing constraints resolution.
• Experience diagnosing DCD/MPW violations and generating ECOs.

Responsibilities

• Close physical design to SOC level, collaborating with contacts.
• Use Innovus, Primetime to perform floorplanning, place-and-route, and timing closure.
• Analyze power, area, timing, and DRC to guide design decisions.
• Develop methodologies for faster design closure and performance improvements.

Education

Master’s degree in Electrical Engineering or related field

Tools

Synopsys ICC

Cadence Innovus

Primetime

Job description

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Austin, Texas. Work on closing the physical design, EMIR, Physical verification, and timing closure. Collaborate with the partition level or SOC level point of contact to make sure the design progresses to closure and if there are any issues while integrating design to SOC level. Use tools like Innovus, voltus and Primetime to design the partition level and interact with the edi company which develops these tools for any enhancements and bugs. Analyze the different matrices of the design like power, area, timing, and DRC to make a decision and evaluate the design for better performance. Work on developing different methodologies for better performance and faster design closure. 40 hours/week.

Minimum Qualifications

• Master’s degree or foreign equivalent in Electrical Engineering or related field and 3 years of experience in the job offered or related occupation
• Experience and/or education must include:
• Using customized scripting in Tcl, Perl, or Python to accelerate physical design closure
• Optimizing leakage power in post route timing tool such as Primetime
• Utilizing a place and route tool including Synopsys ICC or Cadence Innovus for physical design work including floorplanning and place and route implementation work.
• Optimizing power, timing, and area with flow adjustments to improve QoR
• Diagnosing timing constraint issues and provide feedback for needed exceptions
• Understanding localized changes to the clock tree to help close timing
• Diagnosing and resolving DCD (duty-cycle distortion) and MPW (min pulse-width) violations to ensure we have quality clock signals arriving to our flops and macros
• Utilizing static timing and noise analysis allowing resolution of violations that are not fixed by our automated tools.
• Utilizing a PTSI or a similar timing engine to generate ECOs to close timing

Preferred Qualifications

• N/A

This position is not subject to the application limits.

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