ASIC Physical Design Engineer

Jobtailor; Colorado; On-site; USD 140,000 - 210,000; Full time

Job summary

Jobtailor seeks an experienced ASIC Physical Design Engineer in Colorado to lead end-to-end implementation from RTL to GDSII. You will plan floorplanning, power planning, P&R, clock tree synthesis, and routing, ensuring timely, heat-aware, and manufacturable tapeouts.

You will drive timing closure through multi-mode/multi-corner analyses, perform signoff checks, and collaborate with RTL, verification, DFT, and packaging teams. Strong scripting is essential.

Qualifications

• BS in Electrical Engineering or equivalent.
• 5+ years hands-on ASIC physical design from RTL to GDS.
• Experience with floorplanning, place-and-route, clock tree synthesis, routing, and design closure.
• RTL-to-GDSII flow knowledge; resolve congestion, timing, power, area, signal integrity.

Responsibilities

• Execute ASIC physical design from RTL to verified GDS.
• Drive place-and-route execution using industry-standard tools.
• Perform static timing analysis and timing verification across modes/corners.
• Support physical signoff: DRC, LVS, extraction, IR drop, electromigration, SI analysis.
• Collaborate with RTL, verification, DFT, analog, packaging, and product teams to ensure timing-closed, manufacturable tapeout.
• Develop and maintain scripts/flows documenting improvements to physical design methodology.

Skills

ASIC design expertise

Scripting & automation

Cross-team collaboration

Education

BS in Electrical Engineering

Tools

Cadence

Synopsys

Siemens EDA

Tcl

Python

Perl

Shell scripting

Job description

• Execute ASIC digital physical design implementation from RTL or gate-level netlist through GDSII, including floor-planning, placement, clock tree synthesis, routing, and design closure.
• Drive place-and-route execution using industry-standard EDA tools, optimizing designs for timing, power, area, signal integrity, and routability.
• Perform static timing analysis and timing verification across multiple modes and corners, resolving setup, hold, clocking, and constraint-related issues to achieve timing closure.
• Support physical signoff activities, including DRC, LVS, formal equivalence checking, extraction, IR drop, electromigration, and signal integrity analysis.
• Collaborate with RTL design, verification, DFT, analog, packaging, and product architecture teams to resolve implementation issues and ensure a timing-closed, manufacturable, tapeout-ready design.
• Develop and maintain scripts, flows, documentation, and review materials that improve physical design methodology, automation, quality, and schedule predictability.

Requirements

• BS in Electrical Engineering or equivalent experience.
• 5+ years of hands-on experience ASIC physical design from RTL to verified GDS.
• Hands-on experience with ASIC or SoC physical design implementation, including floorplanning, power planning, place-and-route, clock tree synthesis, routing, and design closure.
• Working knowledge of RTL-to-GDSII physical design flows and the ability to resolve implementation issues related to congestion, timing, power, area, and signal integrity.
• Experience with static timing analysis, timing constraints, multi-mode multi-corner timing verification, and timing closure at the block or SoC level.
• Familiarity with physical signoff checks and related debug activities, including DRC, LVS, extraction, formal equivalence checking, IR drop, electromigration, and crosstalk analysis.
• Proficiency with industry-standard physical design and timing tools from vendors such as Cadence, Synopsys, or Siemens EDA.
• Strong scripting and automation skills using Tcl, Python, Perl, or shell scripting to support physical design flows, debug, reporting, and methodology improvement.
• Provide feedback to RTL and packaging design teams to improve design hand-off quality and standard work processes.
• Basic knowledge of industry standard ECO practices.

Core Competencies

Demonstrates expertise in ASIC digital physical design implementation, including RTL to GDSII processes, static timing analysis, and physical signoff activities. Proficient in scripting and automation to enhance design methodologies and collaboration across engineering teams.

Highest-signal resume keywords

• ASIC Physical Design Implementation
• Static Timing Analysis
• Physical Signoff Checks
• Scripting and Automation Skills
• Industry-Standard EDA Tools

ATS Optimization Keywords

Hard Skills

• ASIC Design
• Floorplanning
• Place-and-Route
• Clock Tree Synthesis
• Routing
• Timing Closure
• DRC
• LVS
• IR Drop Analysis
• Electromigration

Industry Keywords

• RTL
• GDSII
• SoC
• Timing Constraints
• Multi-Mode Verification
• Congestion Resolution
• Signal Integrity
• ECO Practices

Tools & Technologies

• Cadence
• Synopsys
• Siemens EDA
• Tcl
• Python
• Perl
• Shell Scripting