PERC ESD & Reliability EDA Tools Lead

Intel Corporation; Santa Clara (CA); On-site; USD 150,000 - 285,000; Full time

Job summary

Intel Corporation in the United States seeks an experienced ESD/LU engineer to develop rule decks and DRMs for cutting-edge PDKs. You will work with design, reliability, and CAD teams plus external EDA vendors to define features, implement tests, and drive automation in QA processes.

The role emphasizes cross-functional leadership, strong problem-solving, and the ability to guide initiatives across sites, contributing to faster time-to-market for Intel’s advanced technologies.

Qualifications

• Master's degree or PhD in Electrical Engineering or Computer Engineering.
• 2+ years' experience with ESD PERC rule decks/runset development and debugging.
• 2+ years' experience in scripting for QA and flow automation.
• 4+ years' experience with reliability/DRC tools.

Responsibilities

• Develop ESD/LU rule decks aligned with DRM and reliability requirements.
• Create and maintain reliability ESD and LU design rule methodologies and specifications.
• Collaborate with internal design, reliability, and CAD teams and external EDA vendors.
• Build and execute test cases for rule debugging, validation, and signoff.
• Define QA requirements and drive automation to improve robustness and efficiency.
• Lead innovation to enhance ESD/LU verification automation and tools.
• Identify and analyze ESD/LU design problems and drive practical solutions.

Skills

ESD rule deck experience

Scripting for QA automation

Education

Master's degree or PhD in Electrical or Computer Engineering

Job description

Intel Corporation in the United States seeks an experienced ESD/LU engineer to develop rule decks and DRMs for cutting-edge PDKs. You will work with design, reliability, and CAD teams plus external EDA vendors to define features, implement tests, and drive automation in QA processes.

The role emphasizes cross-functional leadership, strong problem-solving, and the ability to guide initiatives across sites, contributing to faster time-to-market for Intel’s advanced technologies.