Sr. EDA Tools Engineer - PERC ESD

Intel Corporation; Santa Clara (CA); On-site; USD 150,000 - 285,000; Full time

Job summary

Intel Corporation in the United States seeks an experienced ESD/LU engineer to develop rule decks and DRMs for cutting-edge PDKs. You will work with design, reliability, and CAD teams plus external EDA vendors to define features, implement tests, and drive automation in QA processes.

The role emphasizes cross-functional leadership, strong problem-solving, and the ability to guide initiatives across sites, contributing to faster time-to-market for Intel’s advanced technologies.

Qualifications

• Master's degree or PhD in Electrical Engineering or Computer Engineering.
• 2+ years' experience with ESD PERC rule decks/runset development and debugging.
• 2+ years' experience in scripting for QA and flow automation.
• 4+ years' experience with reliability/DRC tools.

Responsibilities

• Develop ESD/LU rule decks aligned with DRM and reliability requirements.
• Create and maintain reliability ESD and LU design rule methodologies and specifications.
• Collaborate with internal design, reliability, and CAD teams and external EDA vendors.
• Build and execute test cases for rule debugging, validation, and signoff.
• Define QA requirements and drive automation to improve robustness and efficiency.
• Lead innovation to enhance ESD/LU verification automation and tools.
• Identify and analyze ESD/LU design problems and drive practical solutions.

Skills

ESD rule deck experience

Scripting for QA automation

Education

Master's degree or PhD in Electrical or Computer Engineering

Job description

Job Details

Job Description

Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone. Want to learn more? Visit our YouTube Channel or the link below.

Life at Intel

This position is within the Design Technology Platform (DTP) organization. At Intel, DTP is one of the key pillars enabling Intel to deliver winning products in the marketplace. The PERC ESD development team within this organization is looking for individuals who will be responsible to develop PERC ESD rule decks for latest Intel technologies. Your work will directly enable design teams to get to market faster with leadership products on cutting edge technologies. As part of the DTP/Process Design Kit (PDK) group, you will join a highly motivated team of top-notch engineers solving challenging technical problems enabling PDKs for Intel's most advanced process technologies and drive PDKs towards industry standard methods and ease of use for the end customers.

Responsibilities

• Develop ESD/LU rule decks aligned with the ESD Design Rule Manual (DRM) and reliability requirements.
• Create and maintain reliability ESD and LU design rule methodologies and specifications.
• Collaborate with internal design, reliability, and CAD teams as well as external EDA vendors to define and implement new tool features and requirements.
• Build and execute test cases for rule debugging, validation, and signoff.
• Define QA requirements and drive related automation to improve robustness and efficiency of rule checks.
• Lead innovation initiatives to enhance existing ESD/LU verification automation, tools, and methodologies.
• Identify and analyze ESD/LU design problems, define root causes, and drive practical solutions across teams.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences.

Minimum Qualification

• Master's degree or PhD in Electrical Engineering or Computer Engineering.
• 2+ years' experience with ESD PERC rule decks/runset development and debugging (or equivalent reliability/DRC tools).
• 2+ years' experience in scripting (e.g., Python, Tcl, Perl, or similar) for QA and flow automation.

Preferred Requirements

• 4+ years' experience with reliability/DRC tools.
• Industry experience in physical design verification (reliability, device physics, process technology, and design rules, extraction or related domains).
• Creative, independent, and "out of the box" thinker with strong analytical and problem-solving abilities.
• Strong knowledge of ESD/LU PreSi models (HBM, CDM), I\/O design, and related methodologies.
• Strong attention to detail and excellent organization skills.
• Ability to connect the dots across domains and propose cross disciplinary optimal solutions.
• Self-drive with strong leadership skills; able to influence and align internal and external stakeholders.
• Excellent written and verbal communication skills; able to present complex technical concepts clearly and concisely.
• Proven success working with cross functional and cross site teams, with the ability to influence multiple internal and external partners.
• Demonstrated ability to work in a fast paced, team-oriented environment and drive issues to closure.
• Proven ability to work effectively in a dynamic, team-oriented environment.
• Experience driving cross functional and industrywide initiatives or task forces.

Benefits At Intel

Our total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole discretion.

Job Type

Experienced Hire

Shift

Shift 1 (United States of America)

Primary Location

US, Oregon, Hillsboro

Additional Locations

US, Arizona, Phoenix

US, California, Santa Clara

US, Texas, Austin

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $149,600.00 - 284,580.00 USD

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.