PCVD Process Engineer: Yield & DOE Optimization

Micron; Boise (ID); On-site; USD 85,000 - 125,000; Full time

Job summary

Micron Idaho Semiconductor Manufacturing (Triton) LLC is hiring for a process engineer to create, develop, and optimize deposition processes in the semiconductor fab. You will drive yield improvements, cost reductions, and productivity while solving complex process challenges.

The role requires a Master’s degree plus 5 years of related experience, plus strong skills in CVD/ALD or PVD, DRAM process integration, data analysis with JMP or Python, and SPC/FDC-driven quality control.

Qualifications

• Master's degree in Materials Science, Chemical Engineering or related field with 5 years of experience.
• Experience with CVD/ALD or PVD thin-film deposition and process qualification.
• Knowledge of DRAM fabrication and process integration.

Responsibilities

• Create, develop, and optimize processes to improve product quality, drive yield improvements, cost reduction, productivity improvement and risk management.
• Identify, diagnose and resolve process-related problems by applying failure analysis, FMEA, 8D, or the SPC/FDC methodology.
• Coordinate and carry out process, equipment and material evaluation/optimization to implement changes at process step, lead and participate in yield improvement and cost optimization activities, handle new process baseline qualifications and manage, audit and collaborate with material suppliers to achieve quality, cost, and risk mitigation objectives.
• Supervise the health of assigned processes, ensure high-quality output, and provide proactive redundancy plans for bottlenecks that could impact Fab cycle time or turns.

Skills

DRAM fabrication knowledge

DOE for multi-variable optimization

SPC/FDC systems

Process troubleshooting and yield

Cross-functional collaboration

Education

Master's degree in Materials Science or Chemical Engineering

Tools

JMP

Python

Job description

Micron Idaho Semiconductor Manufacturing (Triton) LLC is hiring for a process engineer to create, develop, and optimize deposition processes in the semiconductor fab. You will drive yield improvements, cost reductions, and productivity while solving complex process challenges.

The role requires a Master’s degree plus 5 years of related experience, plus strong skills in CVD/ALD or PVD, DRAM process integration, data analysis with JMP or Python, and SPC/FDC-driven quality control.