Paid Summer Internship - Digital Design Engineer Intern

Credo; San Jose (CA); On-site; USD 25,003 - 35,610; Part time

Benefits offered by this job

Meaningful projects

Competitive compensation

Growth opportunities

Job summary

A technology company in California is seeking a motivated Digital Design Engineering Intern to join the Internal R&D team. In this internship, you will collaborate with engineers to develop high-speed SerDes and DSP-based architectures. Responsibilities include implementing RTL modules, developing behavioral models, and supporting verification efforts. Candidates should be pursuing a degree in Electrical Engineering or related fields, with skills in SystemVerilog, MATLAB, and Python. This role offers an hourly pay of $22, starting in May/June.

Qualifications

• Pursuing a degree in Electrical Engineering or Computer Engineering.
• Experience in digital design, DSP, or communication systems.
• Proficiency in SystemVerilog, MATLAB, Python, or C/C++.

Responsibilities

• Implement and verify RTL modules for SerDes and DSP.
• Collaborate with analog teams on high-speed transceiver designs.
• Develop behavioral models for system components.

Skills

SystemVerilog/Verilog

MATLAB

Python

C/C++

Analytical skills

Problem-solving skills

Education

Currently pursuing a BS, MS, or PhD in Electrical Engineering or related field

Tools

EDA flows

FPGA prototyping

Simulation tools

Job description

A technology company in California is seeking a motivated Digital Design Engineering Intern to join the Internal R&D team. In this internship, you will collaborate with engineers to develop high-speed SerDes and DSP-based architectures. Responsibilities include implementing RTL modules, developing behavioral models, and supporting verification efforts. Candidates should be pursuing a degree in Electrical Engineering or related fields, with skills in SystemVerilog, MATLAB, and Python. This role offers an hourly pay of $22, starting in May/June.