A leading technology firm in San Jose is seeking an RTL Intern to help design microarchitecture and implement logic in Verilog. This role allows you to work on cutting-edge machine learning architectures and participate in the full design cycle. Ideal candidates are pursuing a degree in electrical or computer engineering, understand digital logic, and have a passion for learning about transformers. The internship is paid and provides generous housing support for those relocating.
Qualifications
Must be in a related degree program.
Capability to learn quickly in a fast-paced environment.
Responsibilities
Help design microarchitecture and implement logic in Verilog.
Contribute to RTL block development.
Participate in the full design cycle.
Skills
Familiarity with high-speed digital logic
Exposure to ASIC or SoC design concepts
Familiarity with SystemVerilog
Familiarity with Python
Familiarity with verification work
Ability to learn quickly about transformers
Education
Progress towards a Bachelor’s, Master’s, or PhD in electrical engineering or a related field
Tools
UVM
Job description
A leading technology firm in San Jose is seeking an RTL Intern to help design microarchitecture and implement logic in Verilog. This role allows you to work on cutting-edge machine learning architectures and participate in the full design cycle. Ideal candidates are pursuing a degree in electrical or computer engineering, understand digital logic, and have a passion for learning about transformers. The internship is paid and provides generous housing support for those relocating.