Package & SI/PI - Signal and Power Integrity Engineer

Eliyan Corporation; San Francisco (CA); On-site; USD 120,000 - 150,000; Full time

Benefits offered by this job

Excellent benefits

Fun work environment

Job summary

Eliyan Corporation in San Francisco is seeking a Signal and Power Integrity Engineer to develop packaging solutions for chiplet interconnects. This role involves working with a cross-functional team and leading simulation efforts for advanced packaging technologies.

The ideal candidate will have a BS in EE, 5 years of experience in signal and power integrity, and be proficient with various simulation tools. Eliyan offers an exciting work environment and excellent benefits.

Qualifications

• Expertise in signal integrity and power integrity simulation methodologies.
• Experience with simulation tools such as HFSS, Q3D, Siwave, etc.
• Knowledge of using lab equipment like Vector Network Analyzer and High-Frequency Oscilloscope.

Responsibilities

• Work closely with analog circuit designers to define IO requirements.
• Conduct pre-layout and post-layout channel simulation and optimization.
• Use driver/receiver models for transient channel simulation.

Skills

Signal integrity simulation

Power integrity simulation

Simulation tools (HFSS, Q3D)

Lab equipment proficiency

Education

BS degree in EE or equivalent

MS degree in EE or equivalent

Tools

HFSS

Q3D

Siwave

PowerDC

PowerSI

ADS

Spectre

HSPICE

Allegro

Job description

Join the leading chiplet startup from the ground floor! As a Signal and Power Integrity Engineer, you will provide packaging solutions for chiplet interconnects in a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet-based systems with best-in-class power, area, manufacturability, and design flexibility. You will be responsible for design, modeling, manufacturing, assembly, and testing of traditional and advanced packaging for Eliyan’s chiplet solutions. You will work with a cross‑functional team of industry experts that operate from first principles, innovate and push the envelope to create high‑volume and high‑performance manufacturable products. We offer a fun work environment with excellent benefits.

Key Responsibilities

• Working closely with analog circuit designers to understand and define IO requirements co‑designed with the channel
• Responsible for pre‑layout and post‑layout channel simulation and optimization to achieve the best performance
• Using driver/receiver models to run transient channel simulation, inspect eye diagrams, and improve the performance
• Applying best practices for the design of power delivery networks, extracting models, and performing DC/AC/transient simulations
• Understanding substrate and interposer manufacturing design rules, assembly requirements, and driving the layout engineers to implement them
• Performing measurements in the lab, correlating with simulation, identifying issues and providing solutions

Qualifications

• Expertise in signal integrity and power integrity simulation methodologies
• Experience with simulation tools such as HFSS, Q3D, Siwave, PowerDC, PowerSI, ADS, Spectre, HSPICE, Allegro
• Knowledge of using lab equipment such as Vector Network Analyzer, Spectrum Analyzer, High‑Frequency Oscilloscope
• BS degree in EE or equivalent, with 5 years of experience
• Will not relocate for this role a this time and onsite required

Ideal Qualifications

• Previous experience with IC packaging, manufacturing, and advanced package design
• Knowledge of SERDES design, IBIS-AMI model creation
• MS degree in EE or equivalent, with 7 years of experience