Package Layout Engineer

The Rundown AI, Inc.; Santa Clara (CA); On-site; USD 165,000 - 225,000; Full time

Job summary

An innovative startup is on the lookout for a skilled Package Layout Engineer to join their dynamic team. This role offers the opportunity to work on cutting-edge semiconductor packaging designs, focusing on heterogeneous integration and advanced packaging architectures. The ideal candidate will collaborate with cross-functional teams to ensure designs meet manufacturing and assembly requirements. With a competitive salary and equity options, this position promises to be both rewarding and impactful in shaping the future of photonic fabric solutions. If you are passionate about technology and eager to contribute to groundbreaking projects, this is the perfect opportunity for you.

Qualifications

• Minimum 4 years of experience in semiconductor packaging design.
• Experience with advanced packaging design tools and 2.5D/3D technologies.

Responsibilities

• Support layout studies for package design feasibility.
• Engage with substrate manufacturing and OSAT assembly.

Skills

Semiconductor Packaging Design

Cross-functional Collaboration

Problem-solving

Project Management

Signal Integrity

Power Integrity

Education

BS in EE/ECE/MSE/ME/ChemE

Tools

Cadence APD

AutoCAD

Job description

ABOUT THE ROLE

We are seeking an experienced Package Layout Engineer with expertise in heterogeneous integration. The ideal candidate will have a strong background in semiconductor packaging design to drive Celestial AI’s Photonic Fabric Package solutions. This role requires cross-functional design collaboration with multiple engineering groups, such as Packaging, ASIC, AMS, Photonics, and external partners to ensure design for manufacturing, assembly, reliability, and cost.

ESSENTIAL DUTIES AND RESPONSIBILITIES

• Package Design:
  • Support layout studies for package design feasibility at Silicon/organic interposer and substrate level for multi-chip SiP packaging.
  • Support package pinmap and test collateral release for test vehicle and product designs.
• Package Layout Expertise:
  • Support all aspects of package layout based on I/O, SI-PI and form factor requirements, including routing, design for reliability, thermal, mechanical, manufacturability, bumping, substrate, material selection, assembly, and support for testing.
  • Support cross-functional package layout needs.
• 2.5D and 3D Package Design Planning and Execution:
  • Support Silicon interposer and RDL based design layout solutions for advanced packaging architectures.
  • Netlist management for heterogeneous chiplet assemblies using latest EDA solutions.
• Substrate Manufacturing and OSAT Assembly Engagement:
  • Support activities related to substrate manufacturing such as vendor review and tape-out through various substrate suppliers and OSATs.
  • Actively support test vehicle definition and design for assembly test vehicles.

QUALIFICATIONS

• Education: BS in EE/ECE/MSE/ME/ChemE or related disciplines.
• Experience: minimum4 years of experience in Semiconductor Packaging Design of heterogeneous architectures, including silicon interposer and RDL designs.
• Technical Expertise:
  • Experience working with advanced packaging design tools such as Cadence APD.
  • Familiarity with AutoCAD tools and file formats.
  • Layout experience for various 2.5D/3D packaging technologies including InFO, CoWoS, FoCoS and EMIB.
  • Familiarity with cross-functional packaging areas: Si floor plan, package, board layout and architecture, design rules, BOM, enabling material/process technologies, thermal, mechanical, Signal/Power Integrity, design for manufacturing, assembly, reliability, and cost.
  • Familiarity with photonics packaging is a plus but not necessary.
• Substrate Vendor and OSAT Engagement:
  • Experience working with substrate vendors to meet design for manufacturing, yield, and reliability.
  • Experience working with OSATs to meet assembly requirements.
• Industry Knowledge: Familiarity with High Speed Signaling best practices, Signal and Power integrity requirements.
• Soft Skills: Strong analytical, problem-solving, cross-functional collaboration, project management, and technical presentation skills.

PREFERRED QUALIFICATIONS

• Experience in heterogeneous integration, fan-out packaging, chiplet architectures – co-design, layout, and netlist management.
• Familiarity of Signal and Power Integrity.
• Experience in substrate vendor and OSAT assembly engagement to meet manufacturing and assembly requirements.

LOCATION: Santa Clara, CA

For California Location:

As an early stage start up, we offer an extremely attractive total compensation package inclusive of competitive base salary, bonus and a generous grant of our valuable early-stage equity. The target base salary for this role is approximately $165,000.00 - $225,000.00. The base salary offered may be slightly higher or lower than the target base salary, based on the final scope as determined by the depth of the experience and skills demonstrated by candidate in the interviews.