Analog Layout Engineer

Broadaxis; Santa Clara (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

An established industry player is on the lookout for a highly skilled Analog Layout Engineer to join their innovative team. This role involves leading the layout design of high-performance analog cores, utilizing cutting-edge CMOS technology across advanced process nodes. You will apply your extensive experience in analog layout to ensure the successful implementation of silicon chips for mass production. With a focus on collaboration and technical leadership, this position offers a unique opportunity to make a significant impact in the field of integrated circuit design. If you are passionate about driving excellence in analog layout and thrive in a dynamic environment, this is the perfect role for you.

Qualifications

• 10+ years of experience in high-performance analog layout in advanced CMOS process nodes.
• Extensive knowledge of EDA tools from Cadence, Mentor, and Synopsys.

Responsibilities

• Lead the layout design of high-performance analog cores using advanced CMOS process nodes.
• Collaborate with distributed design teams for successful silicon chip implementation.

Skills

Analog Layout Design

High-Speed CMOS

LVS, DRC, ERC Debugging

Floor Planning

Routing

Chip Assembly

Layout Verification

Thermal-Aware Design

FinFET Process Nodes

Communication Skills

Education

Bachelor's Degree in Electrical Engineering

Master's Degree in Electrical Engineering

Tools

Cadence EDA Tools

Mentor Graphics Tools

Synopsys Tools

Job description

Santa Clara, United States | Posted on 11/05/2024

We are seeking a highly experienced Analog Layout Engineer to join our team in Santa Clara, CA. The ideal candidate will be responsible for the layout of high-performance analog cores such as analog-to-digital converters, digital-to-analog converters, PLLs, and transceivers. The role requires expertise in cutting-edge high-speed CMOS integrated circuits across advanced process nodes, including 3nm, 5nm, 7nm, and 16nm. The candidate will lead the IC layout design, ensuring adherence to industry best practices.

Key Responsibilities:

• Lead the layout design of high-performance, high-speed analog cores using advanced CMOS process nodes (3nm, 5nm, 7nm, 16nm).
  
• Set up and debug LVS, DRC, and ERC environments using EDA tools from Cadence, Mentor, and Synopsys.
  
• Perform floor planning, block-level routing, and top-level chip assembly.
  
• Apply high-performance analog layout techniques, including common centroid layout, shielding, dummy devices, and thermal-aware design.
  
• Collaborate with distributed design teams to ensure the successful implementation of silicon chips for mass production.
  
• Provide technical leadership in layout verification, troubleshooting, and optimization.
  

Qualifications:

• 10+ years of experience in high-performance analog layout in advanced CMOS process nodes.
  
• Extensive knowledge of EDA tools from Cadence, Mentor, and Synopsys.
  
• Proven experience with the layout of analog blocks such as ADCs, DACs, PLLs, and references.
  
• Familiarity with FinFET process nodes and advanced layout techniques for electromigration and thermal management.
  
• Strong skills in floor planning, routing, and chip assembly.
  
• Knowledge of skill code and layout automation is a plus.
  
• Excellent written and verbal communication skills.
  
• Self-starter with the ability to define schedules and meet deadlines effectively.