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An innovative enterprise is seeking a Senior Engineer in Package Design to join their Milpitas office. This role involves supporting silicon device development through package selection and evaluation of new packaging technologies. With a focus on high-performance substrates and IC package technologies, you will collaborate with cross-functional teams and utilize advanced simulation tools. This is a fantastic opportunity to contribute to cutting-edge semiconductor solutions in a dynamic environment. If you have a passion for technology and a strong background in semiconductor packaging, this position offers the chance to make a significant impact in the industry.
Description
Socionext Inc. (SNI) is an innovative enterprise that designs, develops, and delivers System-on-Chip solutions to customers worldwide. The company is focused on AR/VR, ADAS, imaging, networking, data storage, and other dynamic technologies that drive today’s leading-edge applications. Socionext combines world-class expertise, experience, and an extensive IP portfolio to provide exceptional solutions and ensure a better quality of experience for customers. Founded in 2015, Socionext Inc. is headquartered in Yokohama and has offices in Japan, Asia, the United States, and Europe to lead its product development and sales activities. Socionext America Inc. (SNA), a wholly owned subsidiary of SNI.
We are seeking a Senior Engineer, Package Design to work from our Milpitas, CA office.
Responsibilities
The Package Engineering function provides support, expertise, and insight to the Silicon device development team through preliminary activities of package selection, routing techniques, and necessary simulation work. The position involves diverse responsibilities, including evaluation of new packaging technology, package recommendation for custom devices, substrate design support, and device/package qualification. You will be reporting to the Director of Package Design (USA) and will work closely with the Package/Manufacturing team in our headquarters (Japan), Marketing, and Engineering teams located in our Santa Clara office during the pre/post sales process.
This position requires experience in the Fabless semiconductor model with a broad knowledge of package technology and manufacturing. Successful candidates will have a deep understanding of a variety of IC package technologies. Candidates should possess specific experience in the following areas: high-performance build-up substrates, flip chip assembly, or 2.5D packaging. Knowledge of Chiplet technology, Optical integrated packages, and experience in extracting/simulating package designs for SI and PI using tools such as HFSS, POWER SI, and other leading tools are essential.
Qualifications
Education
Bachelor’s degree in Electrical Engineering or other semiconductor packaging-related discipline.
Required Experience And Skills
Preferred Experience And Skills
Good knowledge of IC package materials and manufacturing.
Mid-Senior level
Full-time
Engineering, Design, and Other
Semiconductor Manufacturing