Optical Wafer Test Engineer – NPI to Production

Cisco Systems, Inc; Hazlet Township (NJ); On-site; USD 155,000 - 225,000; Full time

Job summary

Cisco Systems, Inc. is seeking a Wafer Test Development Engineer in New Jersey to lead wafer test development for optical transceivers from NPI through production.

You’ll work with cross-functional teams to optimize DFT/DFM, test coverage, and characterization, driving improvements in yield and cost. The role requires 7+ years in semiconductor processes, hands-on experience with ATE systems and Python, and familiarity with QSFP MSA standards.

Qualifications

• BS in Electrical Engineering or similar required.
• Minimum 7 years in semiconductor processes with silicon/optical/photonic wafers; overseas production experience preferred.
• Hands-on with ATE platforms and automated test programming (Python).
• Familiarity with QSFP MSA standards and strong PCB design awareness.
• Proficiency in statistical methods and tools (JMP, Data Conductor, DataPower, Power BI).

Responsibilities

• Develop, validate, and troubleshoot wafer production testing for optical transceiver products.
• Influence DFT/DFM, test coverage, calibration, and architecture during NPI/design.
• Monitor production flow in offshore manufacturing to meet cost, delivery, and yield targets.
• Analyze data to set test limits, optimize yield, and improve test efficiency.
• Provide cross-functional support for product debug and failure analysis.

Skills

ATE platforms (Advantest 93k, Tel, Ter

Python for test programming

Optical switches/OSAs/oscilloscopes/p‑

PCB design & FAB/semiconductor process

Statistical analysis (JMP, DataCon, DP

QSFP MSA experience

Overseas production experience

Education

BS Electrical Engineering

MS Electrical Engineering

Tools

Agile/Omnify configuration management

Job description

Cisco Systems, Inc. is seeking a Wafer Test Development Engineer in New Jersey to lead wafer test development for optical transceivers from NPI through production.

You’ll work with cross-functional teams to optimize DFT/DFM, test coverage, and characterization, driving improvements in yield and cost. The role requires 7+ years in semiconductor processes, hands-on experience with ATE systems and Python, and familiarity with QSFP MSA standards.