NAND Design AI Architect

Micron Memory Malaysia Sdn Bhd; San Jose, Northern (CA, KY); Hybrid; USD 178,000 - 298,000; Full time

Job summary

Micron Technology seeks a Principal Design Engineer in San Jose, CA to lead advanced NAND circuit design, simulation, and optimization. You will influence architecture, drive DTCO considerations, and mentor teams across multiple groups.

Ideal candidates have 8+ years in NAND design, strong analog/mixed-signal design skills, Verilog and Python, plus Cadence and UNIX proficiency. This role offers a competitive US base salary, comprehensive benefits, and equity.

Qualifications

• 8+ years of NAND design relevant proven experience.
• Proficiency in analog/mixed signal circuit design (page buffers, block selectors, Xdecoder, Ydecoder, bias table and waveforms, PDNs).
• Proficiency with Cadence design, LVS/DRC tools and UNIX.
• Excellent teamwork and communication skills.

Responsibilities

• Serve as a technical authority in the analog/core team for NAND projects, solving complex problems.
• Collaborate on architecting NAND Xpath/Ypath, algorithms and waveforms; analyze DTCO and circuits.
• Design, simulate, optimize, and floor plan NAND circuits; perform die size cost/benefit analyses.
• Develop and productize AI-assisted flows for circuit design and verification.

Skills

NAND design

Analog/mixed signal

Verilog

Python scripting

Circuit debugging

Cadence tools

Unix

Education

MS in Electrical Engineering

PhD preferred

Tools

Cadence LVS/DRC

HSPICE/Fast SPICE

Verilog

Job description

Micron Technology seeks a Principal Design Engineer in San Jose, CA to lead advanced NAND circuit design, simulation, and optimization. You will influence architecture, drive DTCO considerations, and mentor teams across multiple groups.

Ideal candidates have 8+ years in NAND design, strong analog/mixed-signal design skills, Verilog and Python, plus Cadence and UNIX proficiency. This role offers a competitive US base salary, comprehensive benefits, and equity.