MTS- RTL Design

Acceler8 Talent; San Francisco (CA); On-site; USD 230,000 - 320,000; Full time

Benefits offered by this job

Equity

Health benefits

Startup environment

Job summary

Acceler8 Talent is seeking a Senior/Principal Microarchitect to lead the data movement architecture for a cutting-edge AI accelerator in San Francisco, CA. You will own data flow through the SoC, define memory hierarchies, interconnects, and scheduling strategies, spanning architecture to first silicon and production.

Leveling depends on technical scope, ownership, and leadership rather than years of experience.

Qualifications

• Proven expertise designing high-performance data movement architectures for advanced SoCs.

Responsibilities

• Architect high-performance data movement pipelines connecting compute, memory, and interconnect resources across the SoC.
• Define and optimize scratchpad memories, buffers, NoC fabrics, crossbars, and scheduling mechanisms.
• Use modeling, simulation, and workload analysis to drive architectural decisions and optimizations.
• Balance performance, power, utilization, and silicon area while making microarchitectural tradeoffs.
• Collaborate with compiler, runtime, kernel, and performance teams for HW-SW integration.
• Evaluate ISA and programming model choices impacting system efficiency.
• Partner with RTL, verification, and physical design during implementation and timing closure.
• Support emulation, silicon bring-up, and post-silicon optimization efforts.
• Investigate and resolve silicon performance issues for future generations.

Skills

Data movement architecture

NoC architectures

Memory systems

Hardware-software co-design

AI accelerators

Performance per watt

Education

MS/PhD in Computer/ Electrical Engineering or CS

Tools

RTL

Simulation

Performance modeling

Job description

Senior / Principal Microarchitect – Data Movement

We're partnering with a well-funded, stealth-mode AI infrastructure startup building a next-generation rack-scale inference platform for the world's most demanding AI workloads. Their custom silicon is designed alongside the surrounding hardware and software stack to maximize inference efficiency at data center scale. By rethinking system architecture from the chip level up, they're tackling some of the industry's biggest bottlenecks in AI infrastructure. This is an opportunity to join a small, elite engineering team where you'll have significant influence on the architecture of a first-of-its-kind AI platform.

About the Role

We're looking for a Senior or Principal Microarchitect to lead the design of the data movement architecture powering a cutting-edge AI accelerator. You'll own critical aspects of how data flows through the SoC, defining memory hierarchies, interconnects, scheduling strategies, and control mechanisms that maximize performance and efficiency. This role spans architecture, microarchitecture, and hardware-software co-design, with ownership extending from early concept through first silicon and production.

Leveling (Senior vs. Principal) is based on technical scope, ownership, and leadership rather than years of experience.

What You'll Do

• Architect high-performance data movement pipelines that efficiently connect compute, memory, and interconnect resources across the SoC.
• Define and optimize key architectural components including scratchpad memories, buffers, Network-on-Chip (NoC) fabrics, crossbars, and scheduling mechanisms.
• Use performance modeling, simulation, and workload analysis to drive architectural decisions and identify optimization opportunities.
• Balance performance, power, utilization, and silicon area while making critical microarchitectural tradeoffs.
• Collaborate closely with compiler, runtime, kernel, and performance engineering teams to ensure efficient hardware-software integration.
• Evaluate ISA and programming model decisions that impact overall system efficiency.
• Partner with RTL, verification, and physical design teams throughout implementation and timing closure.
• Support emulation, silicon bring-up, performance characterization, and post-silicon optimization efforts.
• Investigate and resolve real silicon performance issues, driving improvements across future product generations.

What We're Looking For

• Proven expertise designing high-performance data movement architectures for advanced SoCs.
• Deep understanding of Network-on-Chip (NoC) architectures, memory systems, buffering strategies, crossbars, switching fabrics, and scheduling algorithms.
• Demonstrated experience leading the architecture and implementation of these systems across multiple silicon generations.
• Strong background in AI accelerators, machine learning processors, or other high-performance compute architectures.
• Experience optimizing designs for performance per watt while balancing power, area, and latency constraints.
• Track record of delivering complex silicon from architecture through production.
• Ability to work independently and thrive in a fast-paced startup environment with broad technical ownership.
• MS or PhD in Computer Engineering, Electrical Engineering, Computer Science, or a related field, with approximately 5–10 years of relevant industry experience (or equivalent expertise).

Nice to Have

• Experience with startup or early-stage silicon development programs.
• Background in hardware-software co-design, performance modeling, or compiler interactions.
• Experience supporting RTL implementation, verification, emulation, and post-silicon performance tuning.

Compensation & Benefits

Compensation is highly competitive and determined by level, technical expertise, and overall impact. In addition to salary, the package includes meaningful equity in a rapidly growing startup, comprehensive health benefits, and the opportunity to help build foundational technology alongside an exceptional engineering team.