Senior Microarchitect

Acceler8 Talent; California (MO); On-site; USD 150,000 - 230,000; Full time

Job summary

Acceler8 Talent is partnering with a VC-backed startup reshaping AI infrastructure from first principles. The team focuses on chip- and system-level innovations to boost inference performance and efficiency.

The role requires designing execution pipelines and datapaths, implementing FP16/BF16/FP8/FP4 support, and optimizing for performance, power, and area while collaborating with architecture, compiler, and performance teams.

Qualifications

• Strong background in AI compute or accelerator design evidenced by complex unit designs.
• Experience across multiple generations of process technology.
• Familiarity with RTL and silicon development flows is desirable.

Responsibilities

• Design execution pipelines, scheduling, and control logic.
• Define datapaths, register files, scratchpads, and memory hierarchies.
• Implement support for FP16, BF16, FP8, and FP4 numeric formats.
• Optimize for performance, utilization, power, and area.
• Balance compute throughput with memory bandwidth and SoC constraints.
• Collaborate with architecture, compiler, kernel, and performance teams.
• Analyze and optimize AI workloads; use profiling to guide decisions.
• Support RTL implementation, verification, and timing closure.
• Participate in emulation, debug, bring-up, and post-silicon tuning.

Skills

AI compute

Accelerator design

Matrix pipelines

Vector pipelines

Floating point numerics

Performance per watt

Education

MS or PhD

Job description

Acceler8 Talent is partnered with a well-funded, VC backed startup rethinking AI infrastructure from first principles.

Founded by veterans who've shipped some of the industry's most successful products, this startup is innovating at the chip and system level to deliver an order of magnitude better performance and efficiency for inference workloads.

Responsibilities

• Design execution pipelines, scheduling, and control logic
• Define datapaths, register files, scratchpads, and local memory hierarchies
• Implement support for modern numeric formats including FP16, BF16, FP8, & FP4
• Optimize for performance, utilization, power, and area
• Balance compute throughput with memory bandwidth and SoC constraints
• Work closely with architecture, compiler, kernel, and performance teams
• Analyze and optimize select AI workloads
• Use performance modeling and profiling to guide architecture decisions
• Support ongoing RTL implementation, verification, and timing closure
• Participate in emulation, debug, bring-up, and post-silicon performance tuning

Qualifications

• Strong background in AI compute or accelerator design as evidenced by design of complex units with multiple blocks over multiple generations of process technology
• Deep understanding of:
• Matrix and vector pipelines
• Floating point numerics
• Performance per watt optimization
• Experience in startup or early-stage silicon programs is a plus
• MS or PhD and 5+ years of experience.