Senior Microarchitect

Acceler8 Talent; Santa Clara, Northern (CA, KY); On-site; USD 250,000 - 420,000; Full time

Job summary

Acceler8 Talent is partnering with a VC-backed startup rethinking AI infrastructure from first principles. This role focuses on designing execution pipelines, datapaths, and memory hierarchies for next-generation AI accelerators, with emphasis on FP16/BF16/FP8 formats and efficiency.

You will lead RTL implementation, support timing closure, and collaborate with architecture, compiler, kernel, and performance teams to optimize performance, utilization, power, and area.

Qualifications

• MS or PhD with 5+ years in AI compute or accelerator design.
• Experience delivering real silicon across multiple process generations.
• Strong understanding of matrix and vector pipelines, FP numerics, and quantization.

Responsibilities

• Design execution pipelines, scheduling, and control logic.
• Define datapaths, register files, scratchpads, and local memory hierarchies.
• Implement support for FP16, BF16, FP8, and FP4 formats.
• Optimize for performance, utilization, power, and area.
• Balance compute throughput with memory bandwidth and SoC constraints.
• Lead RTL implementation and support timing closure.
• Collaborate with architecture, compiler, kernel, and performance teams.
• Participate in emulation, debug, bring-up, and post-silicon tuning.

Skills

AI accelerator design

RTL implementation

Performance optimization

Floating point numerics

Quantization

Education

MS or PhD in Electrical Engineering/CS

Job description

Acceler8 Talent is partnered with a well-funded, VC backed startup rethinking AI infrastructure from first principles.

Founded by veterans who've shipped some of the industry's most successful products, this startup is innovating at the chip and system level to deliver an order of magnitude better performance and efficiency for inference workloads.

Responsibilities:

• Design execution pipelines, scheduling, and control logic
• Define datapaths, register files, scratchpads, and local memory hierarchies
• Implement support for modern numeric formats including FP16, BF16, FP8, & FP4
• Optimize for performance, utilization, power, and area
• Balance compute throughput with memory bandwidth and SoC constraints
• Work closely with architecture, compiler, kernel, and performance teams
• Analyze and optimize select AI workloads
• Evaluate ISA / programming model trade-offs
• Use performance modeling and profiling to guide architecture decisions
• Lead RTL implementation
• Support ongoing RTL implementation, verification, and timing closure
• Participate in emulation, debug, bring-up, and post-silicon performance tuning

Qualifications:

• Strong background in AI compute or accelerator design as evidenced by design of complex units with multiple blocks over multiple generations of process technology
• Deep understanding of:
  • Matrix and vector pipelines
  • Floating point numerics
  • Quantization
  • Performance per watt optimization
• Experience delivering real silicon
• Experience in startup or early-stage silicon programs is a plus
• MS or PhD and 5+ years of experience.

If you're looking for massive ownership, huge impact, and the opportunity to build something fundamentally new from the ground up, please apply here or reach out to hear more.