MTS - HIG HBM - ARCHITECTURE

1000 Micron Technology, Inc.; Richardson (TX); On-site; USD 150,000 - 230,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid time-off and holidays

Competitive benefits

Job summary

Micron Technology, Inc. in Richardson, TX, is seeking an HBM IO Design Architecture Engineer to own the end-to-end design quality system for high‑bandwidth memory projects.

You will drive design quality processes, silicon data analysis, and cross‑team data collection to ensure learnings feed back into the next generation design. The ideal candidate has 10+ years in high‑speed IO/clocking design (32Gbps+), strong analog/digital skills, verification, parasitic extractions, and familiarity with

Qualifications

• 10+ years of relevant engineering or design experience in high-speed IO, PLL, Tx/Rx, and clocking
• Strong background in analog and digital IO design and simulation
• Experience with circuit verification and layout parasitic extraction
• Familiar with off-chip protocols such as UCIe, HBM, DDR, PCIe, MIPI, etc
• Excellent documentation and communication skills

Responsibilities

• High-speed IO design architecture for HBM products
• Define and standardize IO design quality process from architecture to silicon
• Correlate silicon measurements and simulation performance for circuit level design analysis
• Contribute to cross group communication to standardize and enable group success
• Solicit input from Standards, CAD, modeling, and verification groups for design quality
• Drive innovation into future memory generation with AI-assisted analytics

Skills

High-speed IO design

Analog and digital design

Design verification

Parasitic extraction

Communication & documentation

Cross-functional collaboration

Education

MS or PhD in EE

Job description

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The High-Performance Integrated Group (HIG) is a division within the Technology and Products Group (TPG). We are dedicated to developing and optimizing High Bandwidth Memory (HBM) solutions for AI and ML applications! Our ultimate goal is to deliver the lowest power per bit solutions in the industry!

Position Overview

We are searching for an HBM IO Design Architecture Engineer to build and own the end-to-end design quality system — including design checklist delivery, silicon data analysis, and cross-team data collection framework — ensuring that silicon learnings are systematically captured and fed back into the project before the next generation design is finalized. The ideal candidate brings hands‑on experience in design execution, simulation to silicon correlation, and cross‑functional methodology development, and embraces AI‑driven analysis and data‑driven decision making to accelerate quality improvement cycles.

Responsibilities

• High-speed IO design architecture for HBM products
• Define and standardize IO design quality process from architecture to silicon
• Work with Product Engineering to correlate silicon measurements and simulation performance for circuit level design analysis
• Contribute to cross group communication to work towards standardization and group success
• Proactively solicit input from Standards, CAD, modeling, and verification groups to ensure the design quality
• Drive innovation into the future Memory generation with multifaceted work environment
• Leverage AI Assisted analytics to accelerate root cause identification from complex multi-variable silicon data

Successful candidates for this position will have:

• Prior industrial experience in high-speed clocking design at 32Gbps+ speed
• Good IO circuit design background with familiarity of both, analog and digital design and simulation experience required
• Experience with circuit verification and optimization including layout verification and parasitic extractions of the circuits
• Familiar with one or more off-chip protocols such as UCIe, HBM, DDR, PCIe, MIPI, etc
• Good understanding on state-of-the-arts device characteristics and hands‑on design experience
• Excellent problem-solving and analytical skills
• Strong documentation skills
• Strong communication skills with the ability to clearly convey sophisticated technical concepts to other design peers both verbally and written
• Prior circuit debug experience through Product Engineering or equivalent preferred
• Knowledge of advanced packaging environments (CoWoS, HBM stack, D2D, etc)
• Required Experience MS or PhD in EE 10+ years of relevant Engineering or Design Engineering experience on high-speed IO, PLL, Tx, Rx, Equalization, clock tree

Micron benefits

• Medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget
• Benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave
• Robust paid time-off program and paid holidays

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.

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