ML ASIC Design Engineer — High-Performance Cores (Hybrid)

Socket.dev; Mountain View (CA); Hybrid; USD 175,000 - 215,000; Full time

Benefits offered by this job

Discretionary bonuses

Equity incentives

Benefits program

Job summary

Waymo's Compute Team is seeking a seasoned hardware engineer to translate high level requirements into hardware features and to design microarchitectures that deliver world‑class ML performance. You will work with researchers and architects, perform power and performance exploration, and collaborate with verification teams to guarantee functional correctness and maximum efficiency.

This full‑time hybrid role reports to a Senior Staff Silicon Engineer and offers a base salary range of $175,000 to

Qualifications

• BS degree in Computer Engineering or equivalent practical experience.
• 5+ years of industry experience with SystemVerilog, ASIC RTL design and microarchitecture.
• 3+ years designing and specifying microarchitectures of high performance computing cores (CPU/GPU/NPU).
• Fluency in at least one high level programming language such as Python, C++.

Responsibilities

• Translate high level requirements into hardware features and design microarchitectures for ML performance.
• Specify and design microarchitectures to deliver world class ML performance.
• Perform power, area and performance exploration and optimization of digital ASIC designs.
• Design high performance execution units, arithmetic circuits and programmable engines.
• Work with verification teams to guarantee functional correctness and performance.

Skills

SystemVerilog

ASIC RTL design

microarchitecture

Python

C++

Education

Bachelor's degree in Computer Engineering

Tools

Chisel (Scala)

Synthesis tools

Power analysis tools

Job description

Waymo's Compute Team is seeking a seasoned hardware engineer to translate high level requirements into hardware features and to design microarchitectures that deliver world‑class ML performance. You will work with researchers and architects, perform power and performance exploration, and collaborate with verification teams to guarantee functional correctness and maximum efficiency.

This full‑time hybrid role reports to a Senior Staff Silicon Engineer and offers a base salary range of $175,000 to