Mixed Signal validation engineer

Intel; Santa Clara (CA); Hybrid; USD 122,440 - 172,860; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Retirement plan

Vacation

Job summary

Intel is seeking a seasoned Engineer to define, develop, and perform pre-silicon functional validation for mixed-signal designs in the US California region. You will apply hardware and software techniques to ensure validation coverage and meet performance, power, and area goals.

You will collaborate with architecture, design, verification, board and manufacturing teams to improve validation strategies and processes for mixed-signal interfaces across Intel products.

Qualifications

• Experience with pre-silicon functional validation for mixed-signal design.
• Ability to develop validation plans and execute validation tasks.
• Review design changes for impact on validation plans and timelines.

Responsibilities

• Define and perform pre-silicon functional validation for mixed-signal designs.
• Develop validation infrastructure and test environments.
• Publish validation reports and communicate findings to teams.

Skills

SystemVerilog/UVM

Validation planning

Debug and triage

Cross-functional collaboration

Education

Bachelor's Degree in Computer Science/Engineering or STEM with 3+ years

Tools

SystemVerilog

OVM/UVM

Job description

Job Details

Job Description:

Note

This role requires regular onsite presence to fulfill essential job responsibilities.

Position Overview

Defines, develops, and performs pre-silicon functional validation for mixed signal design, electronic parts, components, or integrated circuitry required for mixed signal electronic equipment, devices, and other hardware systems. Applies various hardware and software level tools and techniques to ensure validation coverage and that performance, power, and area goals are met.

Key Responsibilities

• Define, develop, and perform pre-silicon functional validation for mixed signal design, electronic parts, components, and integrated circuitry
• Apply hardware and software level tools and techniques to ensure validation coverage and that performance, power, and area goals are met
• Review proposed design changes to assess impact on validation plans, tasks, and timelines
• Develop mixed signal validation methodologies, execute validation plans, and collaborate with other engineers for design optimization, troubleshooting, and failure analysis
• Perform debug to identify root causes and resolve all functional and triage failures for mixed signal design issues
• Test interactions between various mixed signal design features using validation infrastructure
• Develop pre-silicon validation infrastructure (e.g., monitors, behavioral checkers, coverage) and test environments used in validation testing
• Publish mixed signal validation reports summarizing all validation activities performed, review results, and communicate findings to relevant teams
• Work with architecture, design, verification, board, platform, and manufacturing teams to maintain and improve debug, validation test strategy, methodologies, and processes for mixed signal interfaces to meet desired product specifications

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Minimum Qualifications

• Bachelors Degree in Computer Science, Computer Engineering or Electrical Engineering or another STEM related degree with 3+ years' experience OR
• Masters Degree in Computer Science, Computer Engineering or Electrical Engineering or another STEM related degree with 6+ months' experience.

Experience Listed Above Should Be In The Following

• Working on IP or SoC development, verification, or integration using System Verilog/OVM/UVM
• Writing validation plans implement those validation plans using System Verilog

Preferred Qualifications

• 2+ years of experience with DFI/DDR/LPDDR Protocols
• 2+ years of experience with DDR Phy verification or Memory Controller verification

Job Type

Experienced Hire

Shift

Shift 1 (United States of America)

Primary Location

US, California, Folsom

Additional Locations

US, California, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $122,440.00 - 172,860.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.