Memory Subsystem ASIC Design Engineer — New Grad 2026

NVIDIA; Santa Clara (CA); On-site; USD 100,000 - 166,750; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking an ASIC Design Engineer for new college grads in Santa Clara. The role involves designing memory subsystem components for NVIDIA's SOC Interconnects, collaborating with various teams to meet complex specifications.

Qualified candidates will have a BS or MS in Electrical Engineering or related fields, and will be responsible for RTL design, synthesis, and more. The position offers a competitive salary range of $100,000 to $166,750 for Level 1, with eligibility for equity and benefits.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent experience.
• Familiarity with high-speed coherent interconnects and protocol bridges.
• Strong expertise in Verilog or VHDL.

Responsibilities

• Collaborate with design teams to deliver solutions for complex requirements.
• Responsible for micro-architecture and design activities including RTL design.

Skills

Verilog or VHDL proficiency

Scripting language proficiency (e.g., PERL)

Exposure to high-speed coherent interconnects

Experience with multiple clock domains

Knowledge of industry specifications (CHI, CXL, PCI-E)

Education

BS or MS in Electrical Engineering or Computer Engineering

Job description

NVIDIA is seeking an ASIC Design Engineer for new college grads in Santa Clara. The role involves designing memory subsystem components for NVIDIA's SOC Interconnects, collaborating with various teams to meet complex specifications.

Qualified candidates will have a BS or MS in Electrical Engineering or related fields, and will be responsible for RTL design, synthesis, and more. The position offers a competitive salary range of $100,000 to $166,750 for Level 1, with eligibility for equity and benefits.