Memory PHY Validation Engineer - Post-Silicon Bring-Up

Advanced Micro Devices, Inc.; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

Advanced Micro Devices, Inc. in Austin, TX seeks a Memory PHY post-silicon validation engineer to join our memory interface team. You will design and execute post-silicon validation plans, analyze results, and contribute to production readiness.

The role emphasizes collaboration across labs and disciplines, with focus on pre-silicon test plans, PVT characterization, and optimizing power and performance in next-gen memory IP.

Qualifications

• Memory PHY validation experience with familiarity to firmware and memory IP.
• Programming or scripting experience, Python preferred, plus firmware debugging in Linux environments.
• Experience learning/applying new toolsets, frameworks and validation methodologies.

Responsibilities

• Provide post-silicon support for memory interface IP across products.
• Support bring-up from first silicon in lab through initial production.
• Triage observations from silicon validation and coordinate with ATE, Platform, Firmware, and Characterization teams to identify root causes.
• Provide post-silicon expertise in memory design, process, and integration flows.
• Engage in pre-silicon activities by developing comprehensive test plans and running them in emulation environments.
• Characterize memory PHY across PVT to optimize power and performance.

Skills

Memory PHY validation

Python

Firmware debugging

Linux

Education

Bachelors or Masters in CE/EE

Tools

Oscilloscopes

Signal generators

BERT

Logic analyzers

Job description

Advanced Micro Devices, Inc. in Austin, TX seeks a Memory PHY post-silicon validation engineer to join our memory interface team. You will design and execute post-silicon validation plans, analyze results, and contribute to production readiness.

The role emphasizes collaboration across labs and disciplines, with focus on pre-silicon test plans, PVT characterization, and optimizing power and performance in next-gen memory IP.