Memory Circuit Design Engineer — Build & Optimize Memory Macros

Broadcom; Mendota Heights (MN); On-site; USD 91,000 - 146,000; Full time

Benefits offered by this job

Discretionary annual bonus

Equity plan

Medical/dental/vision benefits

Job summary

BroadcomMemory Circuit Design Engineer in Mendota Heights, MN is seeking an energetic engineer to join our Central Engineering Group and contribute to memory compilers and custom macros on cutting-edge process technology.

You will analyze architectures, design blocks at gate/transistor level, simulate circuits, and manage layout integration. A BS in EE with 5+ years in memory or digital circuits is required, with strong scripting and collaboration skills.

Qualifications

• BS in Electrical Engineering and 5+ years of related experience.
• Experience with memory compilers or memory design projects.
• Knowledge of transistor-level circuit behavior and device physics.
• Familiarity with test setups, silicon testing and debugging is a plus.

Responsibilities

• Analyze memory architectures and highlight tradeoffs.
• Design and build memory blocks at gate or transistor level.
• Simulate and analyze circuit designs with transistor-level simulators.
• Extract layout and perform post-layout simulations and verification.
• Floorplan physical implementation and leafcell layout integration.
• Integrate characterization flow to extract timing and power information.
• Develop scripts to automate characterization flow and verification.
• Specify and verify memory models and timing diagrams.
• Document design specifications and silicon-to-model correlations.
• Support silicon debugging and test planning.

Skills

Memory compilers

Custom digital circuits

Transistor-level behavior

Signal integrity

DFT schemes

Automation scripting

Simulation tooling

Communication skills

Multi-tasking

Education

BS in Electrical Engineering

Job description

BroadcomMemory Circuit Design Engineer in Mendota Heights, MN is seeking an energetic engineer to join our Central Engineering Group and contribute to memory compilers and custom macros on cutting-edge process technology.

You will analyze architectures, design blocks at gate/transistor level, simulate circuits, and manage layout integration. A BS in EE with 5+ years in memory or digital circuits is required, with strong scripting and collaboration skills.