Member of Technical Staff, GPU Compiler

SF Tensor Company; San Francisco (CA); On-site; USD 285,000 - 315,000; Full time

Benefits offered by this job

Relocation assistance

Equity and benefits

Job summary

SF Tensor in San Francisco is building the fastest GPU compiler in the world. We seek a Member of Technical Staff for GPU Compiler Engineering to own the end-to-end pipeline—from MLIR dialects to backend code generation and executable binaries.

You will extend MLIR, work on the LLVM backend, and drive performance across training and inference workloads for diverse hardware targets. Relocation assistance is available; base salary ranges from $285,000 to $315,000 with meaningful equity.

Qualifications

• Deep experience in compiler infrastructure (LLVM, MLIR or similar).
• Strong background in GPU architecture and low-level optimization (CUDA, ROCm or similar).
• Hands-on experience with PTX/SASS, GCN/RDNA assembly or other GPU ISAs.
• Familiar with ML compiler stacks (XLA, TVM, Triton, torch.compiler or similar).
• Solid systems programming skills in C++ and/or Rust.
• Proven track record of building production-grade compiler infrastructure.

Responsibilities

• Build and extend MLIR dialects and passes to optimize training and inference workloads.
• Work in our LLVM backend, below ptxas, on instruction selection, scheduling, register allocation and direct cubin emission.
• Expand our search-based compiler infrastructure with agent- and RL-driven program search and formal correctness proofs.
• Implement classic compiler optimizations tuned for large-scale training.
• Create hybrid codegen paths for cases where direct MLIR lowering isn't practical.
• Own testing, benchmarking and performance regression systems, including bit-identical hardware models.
• Collaborate with research and customer workloads to find optimization opportunities.

Skills

LLVM/MLIR

GPU architecture

C++ or Rust

GPU ISA

ML compiler stacks

Systems programming

Tools

LLVM backend

CUDA

ROCm

Job description

We build the fastest GPU compiler in the world. Most compilers have to preserve correctness at every transform,constraining how far they can search, while we prove correctness at the end instead, allowing us to search a far wider space,with agents, with RL, with anything that works and still guarantee the result. It's why we hold #1 on NVIDIA's own kernel benchmarkacross hundreds of production kernels.

We're hiring a Member of Technical Staff for GPU Compiler Engineering to build the machine that does the searching.

You'll be working on the entire pipeline end to end (StableHLO ingestion, MLIR dialects & passes, backend code generation,executable GPU & host binaries). The pipeline already does things worth seeing. Given only a naive attention spec, the search foundFlashAttention v4-level performance on a B300 in about 25 minutes and your job will be to make sure that next time, we beat FlashAttentionwith ease.

You'll have access to better tooling than anywhere else because we own the stack all the way down to the ISA, allowing us to createkernels that others can't even express. For example, our custom LLVM backend emits cubins directly, without ptxas, letting us work oninstruction selection, scheduling, register allocation and stall counts. Our team understands the hardware better than anyone else,to this extent we've built a bit-exact software model of Blackwell's tcgen05 .

You'll be writing kernels that ship immediately on runs such as pre-training AlphaFold v3 at 3.4× the throughput, post-trainingrobotics models on Trainium or running our custom RL rollout engine on TPU at multi-100B parameter scale.

What You'll Do

• You'll build and extend MLIR dialects and passes to optimize training and inference workloads
• You'll work in our LLVM backend, below ptxas, on instruction selection, scheduling, register allocation and direct cubin emission andwork on standing up equivalent depth on AMD, TPU and Trainium targets
• You'll expand our search-based compiler infrastructure, including agent- and RL-driven program search and the formal correctness proofsthat make aggressive search safe
• You'll implement classic compiler optimizations tuned for large-scale training
• You'll create hybrid codegen paths for cases where direct MLIR lowering isn't practical
• You'll own testing, benchmarking and performance regression systems, including bit-identical hardware models
• You'll work closely with our research team and with customer workloads to find the optimization opportunities that matter

What We're Looking For

• Someone with deep experience in compiler infrastructure (LLVM, MLIR or similar)
• Someone with a strong background in GPU architecture and low-level optimization (CUDA, ROCm or similar)
• Someone with hands‑on experience with at least one of: PTX/SASS, GCN/RDNA assembly or other GPU ISAs
• Someone familiar with ML compiler stacks (XLA, TVM, Triton, torch.compiler or similar)
• Someone with solid systems programming skills in C++ and/or Rust
• Someone with a proven track record of building production‑grade compiler infrastructure

Nice to Have

• Someone with experience in autotuning or search-based optimization
• Someone with a background in formal verification, proof assistants or SMT solvers
• Someone with experience writing or maintaining an LLVM backend
• Someone with a background in distributed systems or multi‑device compilation
• Someone who's contributed to open‑source compiler projects
• Someone familiar with large‑scale training infrastructure
• Someone with experience in (Stable)HLO

Why Join Us

Most compiler engineers spend their career inside a constraint they didn't choose, forced to ensure that every transform is correcton it's own. If you've ever wanted to put real search inside a compiler and never had the architectural freedom or the hardware budgetto try it, this is the job for you. This is a chance to work at the very bottom of the stack on a compiler that is already the fastest inthe world, with a direct and measurable effect on the cost of every large training run we touch.

We're a small team operating at frontier scale. We pre‑trained foundation models on 4,000 AMD GPUs as a team of three, designed andbrought up GB300 NVL72 clusters and designed a TOP500 supercomputer.

We believe that hard problems get solved in person and most of our work happens at our office in San Francisco. We offer relocationassistance and, where possible, we'd like you here as often as possible.

The base salary range for this full-time position is $285,000-$315,000, plus meaningful equity and benefits.