Member of Technical Staff, GPU Kernels

SF Tensor; San Francisco (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

SF Tensor is building the fastest GPU compiler and a versatile kernel optimizer. We seek a Member of Technical Staff for GPU Kernel Engineering to push the envelope on what hardware can do before any search runs.

You will write and hand-optimize kernels that execute during pre-training, post-training and inference across NVIDIA, AMD, TPU and Trainium. You will convert kernel learnings into compiler-search structures, with access to an end-to-end stack down to the ISA.

Qualifications

• Track record of hand-writing kernels that beat vendor libraries or are on par with them.
• Strong C++/CUDA or ROCm/HIP low-level programming skills.
• Experience reading GPU ISA and machine-level assembly (PTX/SASS/GCN).
• Familiarity with profiling tools to diagnose microarchitectural bottlenecks.

Responsibilities

• Write and hand-optimize kernels for real workloads to maximize ceiling before search space exploration.
• Profile at microarchitectural level: SM/CU utilization, warp stalls, memory conflicts, register pressure.
• Debug down to clock behavior, thermal throttling and driver paths; ensure correctness with formal proof where applicable.
• Convert hard-won kernel knowledge into structures the compiler can search.
• Work below PTX at the ISA level, reasoning about SASS and cubins for schedules.
• Build performance models, microbenchmarks and tooling to predict kernel behavior.
• Collaborate with the formal correctness team to ship kernels with a formal proof when required.

Skills

Hand-tuned kernels

Low-level GPU programming

C++

CUDA

ISA familiarity

Performance profiling

Tools

Nsight Compute

Nsight Systems

rocprof

omniperf

Job description

At SF Tensor, we're building the future of high-performance compute. We firmly believe that the future of AI depends on the unglamorous: rethinking and rebuilding the stack, all the way down. From the hardware underneath it to the compiler targeting it and the cloud running it. Right now those three things fight each other and that friction shows up as a tax on every researcher trying to build something ambitious. We're here to axe that tax and make compute faster, cheaper and more available. When we succeed, compute will be portable enough that "which cloud, which chip" stop being something you worry about. To achieve this, we are building our Kernel Optimizer, which takes code and finds its fastest possible form for whatever vendor and cluster topology you point it at, automatically, as well as the Model Foundry which manages the runs, makes research easier and moves workloads across clouds and chips as prices and availability ship, instead of leaving you locked into whatever vendor you signed with first. We're backed by Susa Ventures, Y Combinator, along with some great funds and angels including Max Mullen and Paul Graham, as well as founders and executives at Neuralink, Notion and AMD. We're looking for researchers, engineers and organizations who agree with the basic premise: you don't get the next leap in AI without a leap in compute first.

About The Role

We build the fastest GPU compiler in the world. Most compilers have to preserve correctness at every transform, constraining how far they can search, while we prove correctness at the end instead, allowing us to search a far wider space, with agents, with RL, with anything that works and still guarantee the result. It's why we hold #1 on NVIDIA's own kernel benchmark across hundreds of production kernels. We're hiring a Member of Technical Staff for GPU Kernel Engineering to establish and push the envelope on what the hardware can actually do before any search ever runs. To this extent, you'll write and hand-optimize kernels that execute during pre-training, post-training and inference, across NVIDIA, AMD, TPU and Trainium. You'll then take those learnings and convert them into structures the compiler can search: instruction sequences, scheduling strategies, cost signals, to ensure that the ceiling you worked for by hand can become the floor for the search finding kernels everywhere else. You'll have access to better tooling than anywhere else because we own the stack all the way down to the ISA, allowing us to create kernels that others can't even express. For example, our custom LLVM backend emits cubins directly, without a PTX handoff or ptxas doing our scheduling, letting us write kernels that have no expression in CUDA at all. Our team understands the hardware better than anyone else, to this extent we've built a bit-exact software model of Blackwell's tcgen05. You'll be writing kernels that ship immediately on runs such as pre-training AlphaFold v3 at 3.4× the throughput, post-training robotics models on Trainium or running our custom RL rollout engine on TPU at multi-100B parameter scale.

What You'll Do

• You'll write and hand-optimize kernels for real workloads to find the ceiling before the search goes looking for it
• You'll profile at the microarchitectural level: SM and CU utilization, warp stalls, memory bank conflicts, register pressure, instruction throughput, occupancy tradeoffs
• You'll debug down to the clock behavior, thermal throttling and driver paths where the docs are often missing or just wrong
• You'll turn hard-won knowledge into a machine-searchable structure the compiler can explore on it's own
• You'll work below PTX at the ISA-level, reasoning about SASS and cubins to emit schedules PTX has no way to express
• You'll build the performance models, microbenchmarks and tooling that lets us predict kernel behavior
• You'll work alongside the formal correctness team, so that aggressive, unintuitive kernels ship with a formal proof attached

Expect roughly two-thirds of your time on kernels and one-third on turning what you learned into the compiler search space.

What We're Looking For

• Someone with a track record of hand-writing kernels that match or beat vendor libraries
• Someone comfortable reading PTX, SASS, GCN/CDNA ISA or equivalent machine-level assembly
• Someone fluent with low-level profiling tools: Nsight Compute, Nsight Systems, rocprof, omniperf or their equivalent
• Someone with solid systems programming skills in C++ and CUDA or ROCm/HIP with a working understanding of how high-level ML operations map onto the hardware, including where the framework layers get in the way

Nice to Have

• Someone who's worked on compiler backends (MLIR, LLVM, codegen, instruction selection, scheduling)
• Someone who's done research in the areas of superoptimization, program synthesis, formal verification or search-based compilation
• Someone who's worked with silicon beyond NVIDIA (AMD MI-series, TPU, Trainium) or mobile edge GPUs (Metal, Mali, Aderno)
• Someone who's worked on distributed AI training at depth
• Someone with experie...