Low-Power ASIC Verification Engineer — New Grad

NVIDIA; Santa Clara (CA); On-site; USD 100,000 - 190,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA in Santa Clara, CA is seeking an entry-level Low Power Design/Verification ASIC Engineer for 2026. You will collaborate with Low Power Architecture, Design, and Software teams to understand next-generation features and power-aware DV strategies.

You will architect and develop testbenches, infrastructure, and test plans to verify power management for NVIDIA products, and contribute ideas to improve DV methodologies and engage with EDA vendors.

Qualifications

• Recently completed a BS, MS or PhD in Electrical or Computer Engineering, or equivalent experience.
• Understanding of low power design techniques such as multi VT, Clock gating, Power gating, Block Activity Power, and Dynamic Voltage-Frequency Scaling (DVFS).
• Strong knowledge of GPU architecture and related power management DV techniques.
• Experience with Incisive Low-Power or Synopsys VCS NLP.
• Strong debugging skills and experience with Verdi.
• Fluent in Verilog, SystemVerilog, and understanding of UVM.

Responsibilities

• Work closely with Low Power Architecture, Design, and Software teams to understand next generation features.
• Architect/develop testbench, infrastructure, and test plans to verify various power management solutions for NVIDIA products.
• Bring creative ideas that help improve power-aware DV methodologies and influence EDA vendors to improve simulation and debug efficiencies.

Skills

Verilog

SystemVerilog

UVM

Verdi

Python

Perl

C/C++

DVFS

Education

BS/MS/PhD in Electrical/Computer Engineering

Tools

Incisive Low-Power

Synopsys VCS NLP

Makefile scripting

Job description

NVIDIA in Santa Clara, CA is seeking an entry-level Low Power Design/Verification ASIC Engineer for 2026. You will collaborate with Low Power Architecture, Design, and Software teams to understand next-generation features and power-aware DV strategies.

You will architect and develop testbenches, infrastructure, and test plans to verify power management for NVIDIA products, and contribute ideas to improve DV methodologies and engage with EDA vendors.