Lead Yield & Quality Product Engineer

TSMC; San Jose (CA); On-site; USD 120,000 - 170,000; Full time

Job summary

TSMC Arizona seeks a Product Design Engineer for Yield & Quality to join our 5-nm fab in Phoenix. You will lead root-cause analysis for chip yield and performance, perform failure analysis, and collaborate with Fab teams to define corrective actions.

The role emphasizes early-stage design support, device yield optimization, and cross-functional collaboration. A Master’s in Electrical Engineering and US work eligibility are required, with willingness to travel to Taiwan for training.

Qualifications

• US work eligibility and ability to travel to Taiwan for 6–9 months.
• Master’s Degree in Electrical Engineering is required.
• Working knowledge of semiconductor physics, CMOS device operation, and advanced semiconductor manufacturing is preferred.
• Familiar with digital circuit design is preferred.
• Able to work within cross-functional teams.
• Strong problem-solving, communication, and active learning skills.
• Able to work under pressure and mission orientation.

Responsibilities

• Lead team to identify root causes for N5/N4 chip yield and quality issues.
• Analyze CP test bin and data logs to identify failure modes.
• Electrical and physical failure analysis to locate suspect process stages.
• Work with Fab integration or process teams to define corrective actions.
• Trace action implementation to verify effectiveness.
• Provide early-stage design support to ensure smooth tape-out and silicon success.
• Design rule review and DFM/layout reviews for robust product design.
• Yield window characterization and device sweet-spot identification for optimal yield.

Skills

Semiconductor physics

CMOS device operation

Digital circuit design

Cross-functional teamwork

Problem solving

Communication

Active learning

Willing to travel

Education

Master’s degree in Electrical Engineering

Job description

TSMC Arizona seeks a Product Design Engineer for Yield & Quality to join our 5-nm fab in Phoenix. You will lead root-cause analysis for chip yield and performance, perform failure analysis, and collaborate with Fab teams to define corrective actions.

The role emphasizes early-stage design support, device yield optimization, and cross-functional collaboration. A Master’s in Electrical Engineering and US work eligibility are required, with willingness to travel to Taiwan for training.