Product Design Engineer, Yield & Quality

TSMC; Phoenix (AZ); On-site; USD 110,000 - 160,000; Full time

Job summary

TSMC Arizona is seeking a Product Design Engineer to drive early-stage design, yield optimization and root-cause analysis for 5‑nm devices in Phoenix, AZ. You will partner with cross‑functional teams to ensure robust product design, optimize yield and enable smooth tape‑outs.

The ideal candidate has a Master’s in Electrical Engineering, knowledge of CMOS device operation and semiconductor physics, plus strong problem-solving and communication skills.

Qualifications

• Master's degree in Electrical Engineering required.
• Working knowledge of semiconductor physics and CMOS device operation preferred.
• Familiarity with digital circuit design preferred.
• Ability to work in cross-functional teams and communicate technical concepts clearly.
• Strong problem-solving skills and proactive learning ability.
• Willingness to travel and train in Taiwan for 6–9 months.

Responsibilities

• Lead team to identify root cause for N5/N4 chip performance / yield / quality issues.
• Analyze CP test bin / data log to identify failure mode.
• Electrical and physical failure analysis to locate suspect process stage.
• Collaborate with Fab integration or process teams to define corrective actions and solutions.
• Trace action implementation to verify effectiveness.
• Provide early-stage design support to ensure smooth tape-out and Si success.
• Conduct design rule reviews and assessments for robust product design.
• Perform layout review or DFM to enlarge manufacturing window.
• Characterize yield window and identify device sweet spots for best yield.

Skills

Semiconductor physics

CMOS device operation

Digital circuit design

Cross-functional teamwork

Problem solving

Communication

Active learning

Willingness to travel (Taiwan)

Education

Master's Degree in Electrical Engineering

Job description

TSMC Arizona is seeking a Product Design Engineer to drive early-stage design, yield optimization and root-cause analysis for 5‑nm devices in Phoenix, AZ. You will partner with cross‑functional teams to ensure robust product design, optimize yield and enable smooth tape‑outs.

The ideal candidate has a Master’s in Electrical Engineering, knowledge of CMOS device operation and semiconductor physics, plus strong problem-solving and communication skills.