K2 Space Corporation is looking for a Principal Digital ASIC Design Engineer to oversee the design and integration of advanced digital subsystems for wireless SoCs. This role requires significant experience in RTL design, a strong background in DSP development, and the ability to lead complex verification processes. The position is based in the United States, offering a competitive salary range of $190,000 – $285,000 along with a comprehensive benefits package including paid time off and medical coverage.
Qualifications
10+ years of experience in digital ASIC design, with significant ownership of complex subsystems.
Experience in closing full-chip and subsystem timing.
Solid understanding of SoC design flows including clock/power domain crossing.
Responsibilities
Own the architecture and implementation of key digital blocks in wireless SoCs.
Collaborate with system architects to translate high-level DSP algorithms.
Lead verification planning and validation of complex digital subsystems.
Skills
RTL design (SystemVerilog or Verilog)
Micro-architecture definition
DSP development for wireless communication
Strong debugging and problem-solving skills
Education
B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field
Tools
EDA tools (Synopsys, Cadence, Siemens)
Job description
K2 Space Corporation is looking for a Principal Digital ASIC Design Engineer to oversee the design and integration of advanced digital subsystems for wireless SoCs. This role requires significant experience in RTL design, a strong background in DSP development, and the ability to lead complex verification processes. The position is based in the United States, offering a competitive salary range of $190,000 – $285,000 along with a comprehensive benefits package including paid time off and medical coverage.