Lead Digital ASIC Architect for Space-Grade SoCs

K2 Space Corporation; United States; On-site; USD 200,000 - 300,000; Full time

Benefits offered by this job

Comprehensive benefits package including medical, dental, and vision coverage

Paid time off

Paid parental leave

Equity in the company

Job summary

K2 Space Corporation is seeking a Lead Digital ASIC Engineer to design and implement digital subsystems for advanced wireless SoCs. You will manage a team of engineers, contribute significantly to the development of cutting-edge communication systems for satellites, and ensure timely project deliveries. The role requires extensive experience in digital ASIC design and leadership within the space technology sector, along with a robust knowledge of RTL design and microarchitecture development.

Qualifications

• 10+ years of industry experience in digital ASIC design with ownership of complex digital blocks.
• 3+ years of experience leading ASIC design teams or projects.
• Strong proficiency in RTL design tools and methodologies.

Responsibilities

• Lead and manage a team of digital design engineers.
• Manage development schedules, track deliverables, and report status to senior leadership.
• Contribute to design and implementation of microarchitecture and RTL.

Skills

RTL design

Digital ASIC design

Power performance area optimization

Microarchitecture definition

DSP algorithms

Team leadership

Problem-solving

Communication skills

Education

B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field

Tools

SystemVerilog

Verilog

Synopsys

Cadence

Siemens tools

Job description

K2 Space Corporation is seeking a Lead Digital ASIC Engineer to design and implement digital subsystems for advanced wireless SoCs. You will manage a team of engineers, contribute significantly to the development of cutting-edge communication systems for satellites, and ensure timely project deliveries. The role requires extensive experience in digital ASIC design and leadership within the space technology sector, along with a robust knowledge of RTL design and microarchitecture development.