Lead SoC Subsystem Architect

Synopsys, Inc.; Sunnyvale, Northern (CA, KY); Hybrid; USD 200,000 - 300,000; Full time

Job summary

Synopsys, Inc. is seeking a seasoned Subsystem Architect to lead architecture for IP subsystems powering automotive AI, 5G, and IoT. You will translate product ambitions into robust architectures and integrate multiple IP blocks to deliver cohesive subsystems.

You will collaborate across hardware, firmware, software, verification, and physical design teams, driving architectural decisions and verification strategies, with a focus on performance, power, and protocol interoperability.

Qualifications

• BS or MS in Electrical/Computer Engineering or related field.
• 15+ years of semiconductor experience.
• Proven track record delivering complex subsystems to production.
• Expertise with interconnect and protocol standards.
• Excellent written and verbal communication.

Responsibilities

• Define subsystem architectures translating requirements into detailed specs balancing performance, power, area, and security.
• Integrate IP blocks into cohesive subsystems ensuring interoperability and interface compatibility.
• Lead architecture exploration including IP selection and validation using simulation tools.
• Coordinate with SoC architects, verification, software, and physical design teams.
• Define verification requirements for subsystem functionality and protocol compatibility with DV teams.
• Produce architecture documents, guidelines, and implementation requirements.
• Participate in silicon bring-up, debugging, and subsystem performance characterization.

Skills

Subsystem architecture

Verilog/SystemVerilog

SoC/IP integration

Cross-functional leadership

Technical writing

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

UVM

BFM

Simulation tools

AMBA/AXI/PCIe

Verilog tooling

Job description

Synopsys, Inc. is seeking a seasoned Subsystem Architect to lead architecture for IP subsystems powering automotive AI, 5G, and IoT. You will translate product ambitions into robust architectures and integrate multiple IP blocks to deliver cohesive subsystems.

You will collaborate across hardware, firmware, software, verification, and physical design teams, driving architectural decisions and verification strategies, with a focus on performance, power, and protocol interoperability.