Lead SoC Design Engineer

Oho Group; San Francisco (CA); Hybrid; USD 210,000 - 320,000; Full time

Job summary

Oho Group in the San Francisco Bay Area is seeking a Lead SoC Design Engineer to shape the microarchitecture of a next-generation edge AI SoC. You will lead with architecture, software and verification teams and drive the RTL implementation for key subsystems.

This role is offered as a hybrid position with potential remote work within the US and occasional Bay Area travel as needed. You will join early hardware hires defining technical direction and building a team.

Qualifications

• 10+ years’ experience developing complex ASICs.
• Bachelor’s or Master’s degree in Electrical/Computer Engineering.
• Strong knowledge of AMBA protocols (AXI/AXI-S/APB).
• Familiarity with ARM ecosystem and cache-coherency protocols.
• Experience designing SoCs with multiple power domains and UPF.

Responsibilities

• Define and document detailed SoC microarchitecture and collaborate with architecture, software and verification teams.
• Drive performance, power and area (PPA) trade-offs to meet demanding targets.
• Work with verification teams on test plans, emulation and first-pass silicon success.
• Own design-quality activities including Lint, CDC, RDC, SDC and VCLP.
• Ensure designs progress through physical implementation while meeting frequency and power targets.

Skills

SoC design

RTL implementation

AMBA protocols

ARM ecosystem

UPF / power domains

Lint / CDC / RDC / SDC / VCLP

Hardware architecture leadership

First tapeout readiness

Education

Bachelor's or Master’s in EE/CE

Tools

Emulation tools

Job description

Lead SoC Design Engineer - Stealth Startup - San Francisco Bay Area

We have partnered with a well-funded, stealth-mode technology company developing a next-generation computing platform built around a custom, high-performance edge SoC.

Joining as one of the first hardware hires, you'll be responsible for setting technical direction for the design of a high-performance edge-AI SoC, alongside building a team and leading to first tapeout.

You’ll also play a key role in defining the microarchitecture, making critical PPA trade-offs and leading the RTL implementation of key SoC subsystems.

What You’ll Do

• Define and document detailed SoC microarchitecture and work closely with architecture, software and verification teams.
• Drive performance, power and area (PPA) trade-offs to meet demanding product targets.
• Work with verification teams on test plans, emulation and first-pass silicon success.
• Own key design-quality activities including Lint, CDC, RDC, SDC and VCLP.
• Ensure designs can successfully progress through physical implementation while meeting frequency and power targets.

What We’re Looking For

• 10+ years’ experience developing complex ASICs, ideally on advanced process nodes.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering or equivalent experience.
• Strong knowledge of AMBA protocols, particularly AXI, AXI-S and APB.
• Familiarity with the ARM ecosystem and/or cache-coherency protocols.
• Experience designing SoCs with multiple power domains and UPF.

This is a flexible role based in the San Francisco Bay Area. Although hybrid is preferred, there is openness to remote work from across the US with occasional travel into the Bay Area.