Lead Product Engineer

Cadence; San Jose (CA); On-site; USD 115,000 - 213,000; Full time

Benefits offered by this job

401(k) plan with employer match

Employee stock purchase plan

Medical, dental and vision plans

Paid vacation and holidays

Job summary

Cadence Design Systems is seeking a highly motivated engineer to join the Modus Test Product Engineering team, focusing on Design For Test (DFT) and Automatic Test Pattern Generation (ATPG).

You will develop product specs, prototypes and work with R&D and Product Validation to implement and validate features, while assisting field teams and customers in deployment through flows and hands-on debugging.

Qualifications

• BS or MS in electrical engineering or related field as stated in the requirements.
• 6+ years of direct DFT experience or 4+ years with MS.
• Strong knowledge of ATPG, Scan, and iJTAG standards.

Responsibilities

• Develop features in DFT/ATPG and drive product validation.
• Collaborate with R&D, Product Validation and field teams.
• Create flows, presentations and hands-on debug guidance for customers.

Skills

DFT

ATPG

JTAG

IEEE 1687 (iJTAG)

MBIST

LBIST

EDA tools

Education

BS in Electrical Engineering or related field

MS in Electrical Engineering or related field (preferred)

Tools

DFT EDA tools

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence Design Systems is looking for a highly motivated engineer to work with the Modus Test Product Engineering team working on Design For Test (DFT) and Automatic Test Pattern Generation (ATPG).

What You'll Be Doing

• Be part of a team that is going to help drive new product features in DFT & ATPG
• Develop product spec, prototype and work closely with R&D & Product Validation teams in implementation & validation of such features
• Work with field team and customers in helping deploy Modus by developing flows, presentations & hands-on debug

What We Need To See

• BS (or equivalent experience) with 6+ years or MS with 4+ years of direct experience in DFT either in EDA, CAD or design implementation
• Solid understanding of ATPG, Scan, JTAG, IEEE 1687 (iJTAG), MBIST & LBIST
• Need to be aware of latest technologies & innovations in DFT both in EDA and implementation
• Experience in STA, Physical Design, Silicon bringup related to DFT is a plus
• Flexibility/adaptability for working in a highly dynamic environment and engaging with key stakeholders across various teams within and outside of Cadence
• Excellent communication, interpersonal and customer collaboration skills

Ways To Stand Out From The Crowd

• Broad knowledge of DFT domain & how DFT interacts with various other VLSI domains
• Hands-on experience with DFT EDA tools in the industry

The annual salary range for California is $114,800 to $213,200. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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