Lead Memory Design Engineer – DRAM & CMOS

Micron Technology, Inc; Boise (ID); On-site; USD 90,000 - 130,000; Full time

Benefits offered by this job

Comprehensive healthcare plans

Paid time-off

Paid holidays

Family leave

Job summary

Micron Technology, Inc is seeking a Staff Memory Design Engineer in Boise, Idaho, responsible for designing and analyzing digital and analog circuits for memory products. The role requires expertise in CMOS logic and DRAM architecture and involves collaboration across various teams to ensure high-quality solutions. Strong candidates will have relevant degrees and experience with industry-standard tools. Micron offers comprehensive benefits including healthcare and paid time-off.

Qualifications

• Understanding of device reliability and circuit floor planning.
• Proficiency with circuit simulations.
• Strong problem-solving skills.

Responsibilities

• Design and optimize DRAM circuits.
• Collaborate globally across teams.
• Prepare project status reports and lead design reviews.

Skills

CMOS Circuit Design

VLSI

Analog Circuit Design

Cadence Virtuoso

DRAM architecture

Education

BS or MS in Electrical Engineering

Tools

FINESIM

HSPICE

VERILOG

Job description

Micron Technology, Inc is seeking a Staff Memory Design Engineer in Boise, Idaho, responsible for designing and analyzing digital and analog circuits for memory products. The role requires expertise in CMOS logic and DRAM architecture and involves collaboration across various teams to ensure high-quality solutions. Strong candidates will have relevant degrees and experience with industry-standard tools. Micron offers comprehensive benefits including healthcare and paid time-off.